Inventor · disambiguated record
Ho-Yin Yiu
Also filed as: YIU HO-YIN
28 granted patents·5 pending applications·115 citations·filing 1998–2022
95Inventor score
Top patents by PatentIndex Score
33 records- 0186US10056419B2Chip package having chip connected to sensing device with redistribution layer in insulator layerXINTEC INC·Filed 2018·Granted Aug 21, 2018·4 cites·20 claims
- 0284US9935148B2Method for forming chip package having chip connected to sensing device with redistribution layer in insulator layerXINTEC INC·Filed 2016·Granted Apr 3, 2018·4 cites·20 claims
- 0383US7323784B2Top via pattern for bond pad structureTAIWAN SEMICONDUCTOR MFG·Filed 2005·Granted Jan 29, 2008·14 cites·12 claims
- 0482US10157875B2Chip package and method for forming the sameXINTEC INC·Filed 2015·Granted Dec 18, 2018·4 cites·34 claims
- 0580US9543233B2Chip package having a dual through hole redistribution layer structureXINTEC INC·Filed 2015·Granted Jan 10, 2017·3 cites·9 claims
- 0675US9640405B2Chip package having a laser stop structureXINTEC INC·Filed 2015·Granted May 2, 2017·2 cites·10 claims
- 0775US9406578B2Chip package having extended depression for electrical connection and method of manufacturing the sameXINTEC INC·Filed 2015·Granted Aug 2, 2016·2 cites·22 claims
- 0874US8791768B2Capacitive coupler packaging structureYIU HO-YIN·Filed 2012·Granted Jul 29, 2014·4 cites·20 claims
- 0971US9088206B2Power module and the method of packaging the sameYIU HO-YIN·Filed 2012·Granted Jul 21, 2015·3 cites·20 claims
- 1071US6284557B1Optical sensor by using tunneling diodeTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Sep 4, 2001·34 cites·37 claims
- 1168US9437478B2Chip package and method for forming the sameXINTEC INC·Filed 2014·Granted Sep 6, 2016·2 cites·27 claims
- 1263US8981497B2Chip package structure and method for forming the sameYIU HO-YIN·Filed 2012·Granted Mar 17, 2015·0 cites·18 claims
- 1361US5942800AStress buffered bond pad and method of makingTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 24, 1999·25 cites·20 claims
- 1450US12424567B2Chip package and manufacturing method thereofXINTEC INC·Filed 2022·Granted Sep 23, 2025·0 cites·25 claims
- 1550US9780050B2Method of fabricating chip package with laserXINTEC INC·Filed 2016·Granted Oct 3, 2017·0 cites·9 claims
- 1649US9768067B2Chip package and manufacturing method thereofXINTEC INC·Filed 2016·Granted Sep 19, 2017·0 cites·9 claims
- 1745US9812413B2Chip module and method for forming the sameXINTEC INC·Filed 2016·Granted Nov 7, 2017·0 cites·24 claims
- 1842US9831185B2Chip package and fabrication method thereofXINTEC INC·Filed 2016·Granted Nov 28, 2017·0 cites·20 claims
- 1942US8643070B2Chip package and method for forming the sameCHANG SHU-MING·Filed 2011·Granted Feb 4, 2014·0 cites·20 claims
- 2040US6693317B2Optical sensor by using tunneling diodeTAIWAN SEMICONDUCTOR MFG·Filed 2003·Granted Feb 17, 2004·0 cites·4 claims
- 2140US2012146111A1Chip package and manufacturing method thereofCHANG SHU-MING·Filed 2011·Application pending·0 cites
- 2239US9966358B2Chip packageXINTEC INC·Filed 2016·Granted May 8, 2018·0 cites·8 claims
- 2339US6582981B2Method of using a tunneling diode in optical sensing devicesTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 24, 2003·0 cites·4 claims
- 2438US9853074B2Chip scale sensing chip packageXINTEC INC·Filed 2017·Granted Dec 26, 2017·0 cites·10 claims
- 2538US9721911B2Chip package and manufacturing method thereofXINTEC INC·Filed 2015·Granted Aug 1, 2017·0 cites·22 claims
- 2638US8614488B2Chip package and method for forming the sameWEN YING-NAN·Filed 2011·Granted Dec 24, 2013·0 cites·20 claims
- 2737US6258706B1Method for fabricating a stress buffered bond padTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Jul 10, 2001·8 cites·14 claims
- 2837US2016229687A1Chip package and fabrication method thereofXINTEC INC·Filed 2016·Application pending·0 cites
- 2936US2017047455A1Sensing chip package and a manufacturing method thereofXINTEC INC·Filed 2016·Application pending·0 cites
- 3035US6274397B1Method to preserve the testing chip for package's qualityTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 14, 2001·5 cites·37 claims
- 3135US2016204061A1Chip package and fabrication method thereofXINTEC INC·Filed 2016·Application pending·0 cites
- 3235US2016233260A1Chip package and method for forming the sameXINTEC INC·Filed 2016·Application pending·0 cites
- 3325US6180964B1Low leakage wire bond pad structure for integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 30, 2001·1 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →