Inventor · disambiguated record
David Arnold Luick
Also filed as: LUICK DAVID A · LUICK DAVID ARNOLD
107 granted patents·37 pending applications·1,970 citations·filing 1978–2012
99Inventor score
Top patents by PatentIndex Score
144 records- 0196US7487340B2Local and global branch prediction information storageIBM·Filed 2006·Granted Feb 3, 2009·51 cites·16 claims
- 0292US7086058B2Method and apparatus to eliminate processor core hot spotsIBM·Filed 2002·Granted Aug 1, 2006·86 cites·6 claims
- 0390US7174469B2Processor power and energy managementIBM·Filed 2003·Granted Feb 6, 2007·62 cites·43 claims
- 0489US7447879B2Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache missIBM·Filed 2006·Granted Nov 4, 2008·18 cites·7 claims
- 0589US5812817ACompression architecture for system memory applicationIBM·Filed 1996·Granted Sep 22, 1998·163 cites·13 claims
- 0688US7117389B2Multiple processor core device having shareable functional units for self-repairing capabilityIBM·Filed 2003·Granted Oct 3, 2006·52 cites·15 claims
- 0788US6223208B1Moving data in and out of processor units using idle register/storage functional unitsIBM·Filed 1997·Granted Apr 24, 2001·167 cites·9 claims
- 0887US7783860B2Load misaligned vector with permute and mask insertIBM·Filed 2007·Granted Aug 24, 2010·17 cites·13 claims
- 0986US8429350B2Cache line use history based done bit modification to D-cache replacement schemeLUICK DAVID A·Filed 2012·Granted Apr 23, 2013·8 cites·4 claims
- 1086US7461238B2Simple load and store disambiguation and scheduling at predecodeIBM·Filed 2006·Granted Dec 2, 2008·14 cites·6 claims
- 1185US7124318B2Multiple parallel pipeline processor having self-repairing capabilityIBM·Filed 2003·Granted Oct 17, 2006·30 cites·16 claims
- 1285US7089370B2Apparatus and method for pre-fetching page data using segment table dataIBM·Filed 2003·Granted Aug 8, 2006·41 cites·21 claims
- 1384US7882335B2System and method for the scheduling of load instructions within a group priority issue schema for a cascaded pipelineIBM·Filed 2008·Granted Feb 1, 2011·13 cites·3 claims
- 1484US6314493B1Branch history cacheIBM·Filed 1998·Granted Nov 6, 2001·117 cites·33 claims
- 1584US5625835AMethod and apparatus for reordering memory operations in a superscalar or very long instruction word processorIBM·Filed 1995·Granted Apr 29, 1997·122 cites·3 claims
- 1683US8812822B2Scheduling instructions in a cascaded delayed execution pipeline to minimize pipeline stalls caused by a cache missLUICK DAVID A·Filed 2008·Granted Aug 19, 2014·13 cites·14 claims
- 1783US7865769B2In situ register state error recovery and restart mechanismIBM·Filed 2007·Granted Jan 4, 2011·12 cites·16 claims
- 1882US7680985B2Method and apparatus for accessing a split cache directoryIBM·Filed 2007·Granted Mar 16, 2010·11 cites·18 claims
- 1982US7237094B2Instruction group formation and mechanism for SMT dispatchIBM·Filed 2004·Granted Jun 26, 2007·33 cites·21 claims
- 2082US7234017B2Computer system architecture for a processor connected to a high speed bus transceiverIBM·Filed 2005·Granted Jun 19, 2007·14 cites·32 claims
- 2182US7219185B2Apparatus and method for selecting instructions for execution based on bank prediction of a multi-bank cacheIBM·Filed 2004·Granted May 15, 2007·33 cites·20 claims
- 2282US7188227B2Adaptive memory compressionIBM·Filed 2003·Granted Mar 6, 2007·31 cites·22 claims
- 2381US7730283B2Simple load and store disambiguation and scheduling at predecodeIBM·Filed 2008·Granted Jun 1, 2010·9 cites·6 claims
- 2480US7099999B2Apparatus and method for pre-fetching data to cached memory using persistent historical page table dataIBM·Filed 2003·Granted Aug 29, 2006·27 cites·32 claims
- 2580US6473835B2Partition of on-chip memory buffer for cacheIBM·Filed 2002·Granted Oct 29, 2002·26 cites·12 claims
- 2680US6230260B1Circuit arrangement and method of speculative instruction execution utilizing instruction history cachingIBM·Filed 1998·Granted May 8, 2001·91 cites·40 claims
- 2778US8756404B2Cascaded delayed float/vector execution pipelineLUICK DAVID A·Filed 2006·Granted Jun 17, 2014·9 cites·20 claims
- 2878US8169439B2Scalar precision float implementation on the “W” lane of vector unitLUICK DAVID ARNOLD·Filed 2007·Granted May 1, 2012·10 cites·20 claims
- 2977US8001361B2Structure for a single shared instruction predecoder for supporting multiple processorsIBM·Filed 2008·Granted Aug 16, 2011·8 cites·19 claims
- 3075US8332587B2Cache line use history based done bit modification to I-cache replacement schemeLUICK DAVID A·Filed 2009·Granted Dec 11, 2012·6 cites·16 claims
- 3175US8171224B2D-cache line use history based done bit based on successful prefetchable counterLUICK DAVID A·Filed 2009·Granted May 1, 2012·6 cites·9 claims
- 3275US8161271B2Store misaligned vector with permuteLUICK DAVID ARNOLD·Filed 2007·Granted Apr 17, 2012·8 cites·19 claims
- 3375US7941654B2Local and global branch prediction information storageIBM·Filed 2009·Granted May 10, 2011·5 cites·7 claims
- 3475US6912649B2Scheme to encode predicted values into an instruction stream/cache without additional bits/areaIBM·Filed 2002·Granted Jun 28, 2005·19 cites·23 claims
- 3574US7937530B2Method and apparatus for accessing a cache with an effective addressIBM·Filed 2007·Granted May 3, 2011·6 cites·11 claims
- 3673US8140760B2I-cache line use history based done bit based on successful prefetchable counterLUICK DAVID A·Filed 2009·Granted Mar 20, 2012·5 cites·9 claims
- 3773US7487330B2Method and apparatus for transferring control in a computer system with dynamic compilation capabilityIBM·Filed 2001·Granted Feb 3, 2009·19 cites·15 claims
- 3873US6088769AMultiprocessor cache coherence directed by combined local and global tablesIBM·Filed 1996·Granted Jul 11, 2000·70 cites·6 claims
- 3971US7730288B2Method and apparatus for multiple load instruction executionIBM·Filed 2007·Granted Jun 1, 2010·5 cites·26 claims
- 4071US7676656B2Minimizing unscheduled D-cache miss pipeline stalls in a cascaded delayed execution pipelineIBM·Filed 2008·Granted Mar 9, 2010·4 cites·10 claims
- 4171US5805850AVery long instruction word (VLIW) computer having efficient instruction code formatIBM·Filed 1997·Granted Sep 8, 1998·58 cites·15 claims
- 4270US7278011B2Completion table configured to track a larger number of outstanding instructions without increasing the size of the completion tableIBM·Filed 2004·Granted Oct 2, 2007·14 cites·34 claims
- 4369US8135941B2Vector morphing mechanism for multiple processor coresLUICK DAVID A·Filed 2008·Granted Mar 13, 2012·4 cites·20 claims
- 4469US7984270B2System and method for prioritizing arithmetic instructionsIBM·Filed 2008·Granted Jul 19, 2011·4 cites·3 claims
- 4568US5924117AMulti-ported and interleaved cache memory supporting multiple simultaneous accesses theretoIBM·Filed 1996·Granted Jul 13, 1999·53 cites·25 claims
- 4667US6990510B2Wide adder with critical path of three gatesIBM·Filed 2002·Granted Jan 24, 2006·12 cites·16 claims
- 4766US8095779B2System and method for optimization within a group priority issue schema for a cascaded pipelineLUICK DAVID A·Filed 2008·Granted Jan 10, 2012·3 cites·3 claims
- 4866US7984272B2Design structure for single hot forward interconnect scheme for delayed execution pipelinesIBM·Filed 2008·Granted Jul 19, 2011·3 cites·18 claims
- 4966US7870368B2System and method for prioritizing branch instructionsIBM·Filed 2008·Granted Jan 11, 2011·3 cites·4 claims
- 5066US7188130B2Automatic temporary precision reduction for enhanced compressionIBM·Filed 2003·Granted Mar 6, 2007·6 cites·23 claims
Showing the top 50 of 144 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →