Inventor · disambiguated record
Shahriar Ahmed
Also filed as: AHMED SHAHRIAR · AHMED SHAHRIAR S
14 granted patents·2 pending applications·369 citations·filing 1994–2008
93Inventor score
Top patents by PatentIndex Score
16 records- 0194US5434093AInverted spacer transistorINTEL CORP·Filed 1994·Granted Jul 18, 1995·166 cites·25 claims
- 0284US6020244AChannel dopant implantation with automatic compensation for variations in critical dimensionINTEL CORP·Filed 1996·Granted Feb 1, 2000·75 cites·10 claims
- 0381US6384457B2Asymmetric MOSFET devicesINTEL CORP·Filed 1999·Granted May 7, 2002·43 cites·20 claims
- 0479US6297104B1Methods to produce asymmetric MOSFET devicesINTEL CORP·Filed 2000·Granted Oct 2, 2001·23 cites·18 claims
- 0574US6703685B2Super self-aligned collector device for mono-and hetero bipolar junction transistorsINTEL CORP·Filed 2001·Granted Mar 9, 2004·15 cites·14 claims
- 0673US7202514B2Self aligned compact bipolar junction transistor layout and method of making sameINTEL CORP·Filed 2003·Granted Apr 10, 2007·16 cites·12 claims
- 0761US7015085B2Super self-aligned collector device for mono-and hetero bipolar junction transistors and method of making sameINTEL CORP·Filed 2003·Granted Mar 21, 2006·7 cites·24 claims
- 0857US7005359B2Bipolar junction transistor with improved extrinsic base region and method of fabricationINTEL CORP·Filed 2003·Granted Feb 28, 2006·6 cites·15 claims
- 0952US7517768B2Method for fabricating a heterojunction bipolar transistorINTEL CORP·Filed 2003·Granted Apr 14, 2009·6 cites·5 claims
- 1050US7064042B1Self aligned compact bipolar junction transistor layout, and method of making sameINTEL CORP·Filed 2004·Granted Jun 20, 2006·4 cites·5 claims
- 1149US7414298B2Super self-aligned collector device for mono-and hetero bipolar junction transistors, and method of making sameINTEL CORP·Filed 2003·Granted Aug 19, 2008·3 cites·12 claims
- 1244US2006113634A1Bipolar junction transistor with improved extrinsic base region and method of fabricationAHMED SHAHRIAR·Filed 2005·Application pending·0 cites
- 1342US6579771B1Self aligned compact bipolar junction transistor layout, and method of making sameINTEL CORP·Filed 2001·Granted Jun 17, 2003·1 cites·30 claims
- 1442US6458667B1High power PMOS deviceINTEL CORP·Filed 2000·Granted Oct 1, 2002·1 cites·9 claims
- 1541US2009241075A1Test chip validation and development systemAHMED SHAHRIAR·Filed 2008·Application pending·0 cites
- 1636US6177705B1High power PMOS deviceINTEL CORP·Filed 1999·Granted Jan 23, 2001·3 cites·7 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →