Inventor · disambiguated record
Barry J. Flahive
Also filed as: FLAHIVE BARRY · FLAHIVE BARRY J
9 granted patents·476 citations·filing 1978–1997
91Inventor score
Technology areasG06F
Top patents by PatentIndex Score
9 records- 0186US5175829AMethod and apparatus for bus lock during atomic computer operationsHEWLETT PACKARD CO·Filed 1988·Granted Dec 29, 1992·107 cites·9 claims
- 0285US4449183AArbitration scheme for a multiported shared functional device for use in multiprocessing systemsDIGITAL EQUIPMENT CORP·Filed 1981·Granted May 15, 1984·106 cites·11 claims
- 0383US4860244ABuffer system for input/output portion of digital data processing systemDIGITAL EQUIPMENT CORP·Filed 1983·Granted Aug 22, 1989·67 cites·40 claims
- 0469US6286095B1Computer apparatus having special instructions to force ordered load and store operationsHEWLETT PACKARD CO·Filed 1995·Granted Sep 4, 2001·61 cites·8 claims
- 0567US5051885AData processing system for concurrent dispatch of instructions to multiple functional unitsHEWLETT PACKARD CO·Filed 1988·Granted Sep 24, 1991·40 cites·10 claims
- 0665US5167022AMultiprocessor bus locking system with a winning processor broadcasting an ownership signal causing all processors to halt their requestsHEWLETT PACKARD CO·Filed 1990·Granted Nov 24, 1992·47 cites·4 claims
- 0749US4290133ASystem timing means for data processing systemDIGITAL EQUIPMENT CORP·Filed 1978·Granted Sep 15, 1981·13 cites·14 claims
- 0848US6079012AComputer that selectively forces ordered execution of store and load operations between a CPU and a shared memoryHEWLETT PACKARD CO·Filed 1997·Granted Jun 20, 2000·22 cites·8 claims
- 0944US4755936AApparatus and method for providing a cache memory unit with a write operation utilizing two system clock cyclesDIGITAL EQUIPMENT CORP·Filed 1986·Granted Jul 5, 1988·13 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →