Inventor · disambiguated record
Robert L. Farrell
Also filed as: FARRELL ROBERT · FARRELL ROBERT L
32 granted patents·3 pending applications·1,188 citations·filing 1983–2016
97Inventor score
Top patents by PatentIndex Score
35 records- 0194US5640543AScalable multimedia platform architectureINTEL CORP·Filed 1996·Granted Jun 17, 1997·169 cites·9 claims
- 0293US6785829B1Multiple operating frequencies in a processorINTEL CORP·Filed 2000·Granted Aug 31, 2004·92 cites·21 claims
- 0392US4570220AHigh speed parallel bus and data transfer methodINTEL CORP·Filed 1983·Granted Feb 11, 1986·194 cites·21 claims
- 0490US5355467ASecond level cache controller unit and systemINTEL CORP·Filed 1994·Granted Oct 11, 1994·211 cites·9 claims
- 0589US5510740AMethod for synchronizing clocks upon resetINTEL CORP·Filed 1994·Granted Apr 23, 1996·51 cites·9 claims
- 0686US6988211B2System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit fieldINTEL CORP·Filed 2000·Granted Jan 17, 2006·45 cites·23 claims
- 0786US5228134ACache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory busINTEL CORP·Filed 1991·Granted Jul 13, 1993·121 cites·27 claims
- 0879US5293603ACache subsystem for microprocessor based computer system with synchronous and asynchronous data pathINTEL CORP·Filed 1991·Granted Mar 8, 1994·84 cites·18 claims
- 0978US9824412B2Position-only shading pipelineINTEL CORP·Filed 2014·Granted Nov 21, 2017·5 cites·55 claims
- 1076US8643660B2Technique to share information among different cache coherency domainsOFFEN ZEEV·Filed 2012·Granted Feb 4, 2014·2 cites·8 claims
- 1174US4807109AHigh speed synchronous/asynchronous local bus and data transfer methodINTEL CORP·Filed 1987·Granted Feb 21, 1989·58 cites·16 claims
- 1271US8205032B2Virtual machine control structure identification decoderMONDAL SANJOY K·Filed 2011·Granted Jun 19, 2012·3 cites·17 claims
- 1370US5664153APage open/close scheme based on high order address bit and likelihood of page accessINTEL CORP·Filed 1995·Granted Sep 2, 1997·62 cites·16 claims
- 1463US10204051B2Technique to share information among different cache coherency domainsINTEL CORP·Filed 2016·Granted Feb 12, 2019·0 cites·23 claims
- 1563US10078590B2Technique to share information among different cache coherency domainsINTEL CORP·Filed 2016·Granted Sep 18, 2018·0 cites·21 claims
- 1663US9946650B2Technique to share information among different cache coherency domainsINTEL CORP·Filed 2016·Granted Apr 17, 2018·0 cites·24 claims
- 1763US9412195B2Constant buffer size multi-sampled anti-aliasing depth compressionINTEL CORP·Filed 2014·Granted Aug 9, 2016·1 cites·12 claims
- 1861US9569882B2Four corner high performance depth testINTEL CORP·Filed 2013·Granted Feb 14, 2017·1 cites·19 claims
- 1960US9665488B2Technique to share information among different cache coherency domainsINTEL CORP·Filed 2014·Granted May 30, 2017·0 cites·16 claims
- 2059US9035962B2Technique to share information among different cache coherency domainsINTEL CORP·Filed 2013·Granted May 19, 2015·0 cites·7 claims
- 2159US6091426AIntegrating data scaling and buffering functions to minimize memory requirementINTEL CORP·Filed 1997·Granted Jul 18, 2000·30 cites·9 claims
- 2257US7937525B2Method and apparatus for decoding a virtual machine control structure identificationINTEL CORP·Filed 2004·Granted May 3, 2011·4 cites·24 claims
- 2356US9035960B2Technique to share information among different cache coherency domainsOFFEN ZEEV·Filed 2012·Granted May 19, 2015·0 cites·20 claims
- 2456US5519345AReconfigurable interrupt device and methodINTEL CORP·Filed 1995·Granted May 21, 1996·13 cites·11 claims
- 2555US5953411AMethod and apparatus for maintaining audio sample correlationINTEL CORP·Filed 1996·Granted Sep 14, 1999·23 cites·22 claims
- 2654US9035959B2Technique to share information among different cache coherency domainsOFFEN ZEEV·Filed 2008·Granted May 19, 2015·0 cites·25 claims
- 2752US7269711B2Methods and apparatus for address generation in processorsINTEL CORP·Filed 2003·Granted Sep 11, 2007·3 cites·41 claims
- 2847US2010031268A1Thread ordering techniquesDWYER MICHAEL K·Filed 2008·Application pending·0 cites
- 2945US10002455B2Optimized depth buffer cache apparatus and methodINTEL CORP·Filed 2015·Granted Jun 19, 2018·0 cites·22 claims
- 3045US8151061B2Ensuring coherence between graphics and display domainsFARRELL ROBERT L·Filed 2009·Granted Apr 3, 2012·0 cites·22 claims
- 3141US8813083B2Method and system for safe enqueuing of eventsFARRELL ROBERT L·Filed 2011·Granted Aug 19, 2014·0 cites·21 claims
- 3241US5488639AParallel multistage synchronization method and apparatusINTEL CORP·Filed 1993·Granted Jan 30, 1996·16 cites·4 claims
- 3340US2012233439A1Implementing TLB Synchronization for Systems with Shared Virtual Memory Between Processing DevicesGINZBURG BORIS·Filed 2011·Application pending·0 cites
- 3440US2012236010A1Page Fault Handling MechanismGINZBURG BORIS·Filed 2011·Application pending·0 cites
- 3535US7249243B2Control word prediction and varying recovery upon comparing actual to set of stored wordsINTEL CORP·Filed 2003·Granted Jul 24, 2007·0 cites·26 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →