Inventor · disambiguated record
Andrew Strachan
Also filed as: STRACHAN ANDREW · STRACHAN ANDREW D · STRACHAN ANDREW DEREK
27 granted patents·1 pending application·142 citations·filing 1990–2020
95Inventor score
Top patents by PatentIndex Score
28 records- 0190US7180140B1PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such deviceNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 20, 2007·44 cites·15 claims
- 0286US9905428B2Split-gate lateral extended drain MOS transistor structure and processTEXAS INSTRUMENTS INC·Filed 2015·Granted Feb 27, 2018·5 cites·18 claims
- 0385US8445353B1Method for integrating MIM capacitor and thin film resistor in modular two layer metal process and corresponding deviceRAGHAVAN VENKAT·Filed 2009·Granted May 21, 2013·16 cites·4 claims
- 0483US8686502B2Schottky diode integrated into LDMOSTEXAS INSTRUMENTS INC·Filed 2013·Granted Apr 1, 2014·7 cites·8 claims
- 0581US9773777B2Low dynamic resistance low capacitance diodesTEXAS INSTRUMENTS INC·Filed 2016·Granted Sep 26, 2017·3 cites·8 claims
- 0675US11152505B2Drain extended transistorTEXAS INSTRUMENTS INC·Filed 2018·Granted Oct 19, 2021·2 cites·24 claims
- 0775US10431357B2Vertically-constructed, temperature-sensing resistors and methods of making the sameTEXAS INSTRUMENTS INC·Filed 2017·Granted Oct 1, 2019·1 cites·20 claims
- 0874US7067879B1Integration of trench power transistors into a 1.5 μm BCD processNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jun 27, 2006·18 cites·7 claims
- 0972US6548839B1LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliabilityNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 15, 2003·18 cites·9 claims
- 1066US7510944B1Method of forming a MIM capacitorNAT SEMICONDUCTOR CORP·Filed 2007·Granted Mar 31, 2009·3 cites·14 claims
- 1165US11552183B2Transistors with oxide liner in drift regionTEXAS INSTRUMENTS INC·Filed 2020·Granted Jan 10, 2023·0 cites·11 claims
- 1261US10937574B2Vertically-constructed, temperature-sensing resistors and methods of making the sameTEXAS INSTRUMENTS INC·Filed 2019·Granted Mar 2, 2021·0 cites·22 claims
- 1357US10714594B2Transistors with oxide liner in drift regionTEXAS INSTRUMENTS INC·Filed 2017·Granted Jul 14, 2020·0 cites·19 claims
- 1457US9595480B2Method of forming a BICMOS semiconductor chip that increases the betas of the bipolar transistorsTEXAS INSTRUMENTS INC·Filed 2014·Granted Mar 14, 2017·0 cites·16 claims
- 1556US8664076B2Method of forming a robust, modular MIS (metal-insulator-semiconductor) capacitor with improved capacitance densityRAGHAVAN VENKAT·Filed 2011·Granted Mar 4, 2014·1 cites·4 claims
- 1656US7425741B1EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusionNAT SEMICONDUCTOR CORP·Filed 2005·Granted Sep 16, 2008·1 cites·9 claims
- 1755US10153269B2Low dynamic resistance low capacitance diodesTEXAS INSTRUMENTS INC·Filed 2017·Granted Dec 11, 2018·0 cites·20 claims
- 1855US7071513B1Layout optimization of integrated trench VDMOS arraysNAT SEMICONDUCTOR CORP·Filed 2004·Granted Jul 4, 2006·6 cites·14 claims
- 1955US6798641B1Low cost, high density diffusion diode-capacitorNAT SEMICONDUCTOR CORP·Filed 2003·Granted Sep 28, 2004·6 cites·6 claims
- 2054US9831135B2Method of forming a biCMOS semiconductor chip that increases the betas of the bipolar transistorsTEXAS INSTRUMENTS INC·Filed 2017·Granted Nov 28, 2017·0 cites·9 claims
- 2150US7560348B2Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-inNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jul 14, 2009·0 cites·7 claims
- 2249US7192853B1Method of improving the breakdown voltage of a diffused semiconductor junctionNAT SEMICONDUCTOR CORP·Filed 2003·Granted Mar 20, 2007·2 cites·3 claims
- 2347US10748818B2Dynamic biasing to mitigate electrical stress in integrated resistorsTEXAS INSTRUMENTS INC·Filed 2018·Granted Aug 18, 2020·0 cites·8 claims
- 2447US8086979B2Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-inBRISBIN DOUGLAS·Filed 2009·Granted Dec 27, 2011·0 cites·11 claims
- 2546US6646320B1Method of forming contact to poly-filled trench isolation regionNAT SEMICONDUCTOR CORP·Filed 2002·Granted Nov 11, 2003·1 cites·17 claims
- 2636US2013240980A1Schottky diode integrated into LDMOSRAGHAVAN VENKAT·Filed 2012·Application pending·0 cites
- 2734US8541863B2Data retention in a single poly EPROM cellRAGHAVAN VENKAT·Filed 2010·Granted Sep 24, 2013·0 cites·2 claims
- 2828US5045495AForming twin wells in semiconductor devicesINMOS LTD·Filed 1990·Granted Sep 3, 1991·8 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →