Inventor · disambiguated record
Rajasekhar Cherabuddi
Also filed as: CHERABUDDI RAJASEKHAR
25 granted patents·869 citations·filing 1996–2011
97Inventor score
Top patents by PatentIndex Score
25 records- 0194US8468151B2Methods and systems for hardware acceleration of database operations and queries based on multiple hardware acceleratorsBRANSCOME JEREMY L·Filed 2011·Granted Jun 18, 2013·27 cites·8 claims
- 0293US9141670B2Methods and systems for hardware acceleration of streamed database operations and queries based on multiple hardware acceleratorsBRANSCOME JEREMY L·Filed 2011·Granted Sep 22, 2015·22 cites·38 claims
- 0391US6725336B2Dynamically allocated cache memory for a multi-processor unitSUN MICROSYSTEMS INC·Filed 2001·Granted Apr 20, 2004·70 cites·17 claims
- 0482US5884100ALow-latency, high-throughput, integrated cache coherent I/O system for a single-chip processorSUN MICROSYSTEMS INC·Filed 1996·Granted Mar 16, 1999·108 cites·10 claims
- 0580US5996048AInclusion vector architecture for a level two cacheSUN MICROSYSTEMS INC·Filed 1997·Granted Nov 30, 1999·86 cites·16 claims
- 0676US6535966B1System and method for using a page tracking buffer to reduce main memory latency in a computer systemSUN MICROSYSTEMS INC·Filed 2000·Granted Mar 18, 2003·25 cites·8 claims
- 0776US6477622B1Simplified writeback handlingSUN MICROSYSTEMS INC·Filed 2000·Granted Nov 5, 2002·22 cites·18 claims
- 0875US6496917B1Method to reduce memory latencies by performing two levels of speculationSUN MICROSYSTEMS INC·Filed 2000·Granted Dec 17, 2002·26 cites·19 claims
- 0974US6330662B1Apparatus including a fetch unit to include branch history information to increase performance of multi-cylce pipelined branch prediction structuresSUN MICROSYSTEMS INC·Filed 1999·Granted Dec 11, 2001·66 cites·8 claims
- 1074US5854761ACache memory array which stores two-way set associative dataSUN MICROSYSTEMS INC·Filed 1997·Granted Dec 29, 1998·67 cites·20 claims
- 1172US7433351B1Isolation of data, control, and management traffic in a storage area networkBROCADE COMM SYSTEMS INC·Filed 2002·Granted Oct 7, 2008·18 cites·28 claims
- 1268US6134654ABi-level branch target prediction scheme with fetch address predictionSUN MICROSYSTEMS INC·Filed 1998·Granted Oct 17, 2000·53 cites·22 claims
- 1362US5761708AApparatus and method to speculatively initiate primary memory accessesSUN MICROSYSTEMS INC·Filed 1996·Granted Jun 2, 1998·42 cites·14 claims
- 1459US6256729B1Method and apparatus for resolving multiple branchesSUN MICROSYSTEMS INC·Filed 1998·Granted Jul 3, 2001·35 cites·20 claims
- 1558US6918071B2Yield improvement through probe-based cache size reductionSUN MICROSYSTEMS INC·Filed 2001·Granted Jul 12, 2005·10 cites·12 claims
- 1655US5860117AApparatus and method to improve primary memory latencies using an eviction buffer to store write requestsSUN MICROSYSTEMS INC·Filed 1996·Granted Jan 12, 1999·29 cites·12 claims
- 1751US6553435B1DMA transfer method for a system including a single-chip processor with a processing core and a device interface in different clock domainsSUN MICROSYSTEMS INC·Filed 1999·Granted Apr 22, 2003·23 cites·18 claims
- 1849US5938761AMethod and apparatus for branch target predictionSUN MICROSYSTEMS INC·Filed 1997·Granted Aug 17, 1999·21 cites·26 claims
- 1948US6263416B1Method for reducing number of register file ports in a wide instruction issue processorSUN MICROSYSTEMS INC·Filed 1997·Granted Jul 17, 2001·20 cites·4 claims
- 2047US5835947ACentral processing unit and method for improving instruction cache miss latencies using an instruction buffer which conditionally stores additional addressesSUN MICROSYSTEMS INC·Filed 1996·Granted Nov 10, 1998·20 cites·2 claims
- 2146US5944810ASuperscalar processor for retiring multiple instructions in working register file by changing the status bits associated with each execution result to identify valid dataSUN MICROSYSTEMS INC·Filed 1997·Granted Aug 31, 1999·17 cites·4 claims
- 2246US5829010AApparatus and method to efficiently abort and restart a primary memory accessSUN MICROSYSTEMS INC·Filed 1996·Granted Oct 27, 1998·18 cites·12 claims
- 2345US6115810ABi-level branch target prediction scheme with mux select predictionSUN MICROSYSTEMS INC·Filed 1998·Granted Sep 5, 2000·17 cites·25 claims
- 2444US6256709B1Method for storing data in two-way set associative odd and even banks of a cache memorySUN MICROSYSTEMS INC·Filed 1997·Granted Jul 3, 2001·16 cites·17 claims
- 2539US6289441B1Method and apparatus for performing multiple branch predictions per cycleSUN MICROSYSTEMS INC·Filed 1998·Granted Sep 11, 2001·11 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →