Inventor · disambiguated record
Matthew W. Copel
Also filed as: COPEL MATTHEW · COPEL MATTHEW W · COPEL MATTHEW WARREN
65 granted patents·9 pending applications·1,260 citations·filing 1993–2020
99Inventor score
Top patents by PatentIndex Score
74 records- 0198US7618841B2Hydrazine-free solution deposition of chalcogenide filmsIBM·Filed 2006·Granted Nov 17, 2009·56 cites·12 claims
- 0298US7488656B2Removal of charged defects from metal oxide-gate stacksIBM·Filed 2005·Granted Feb 10, 2009·79 cites·10 claims
- 0397US9659249B1Pre-programmed resistive cross-point array for neural networkIBM·Filed 2016·Granted May 23, 2017·29 cites·14 claims
- 0497US7105889B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectricsIBM·Filed 2004·Granted Sep 12, 2006·93 cites·26 claims
- 0597US7094651B2Hydrazine-free solution deposition of chalcogenide filmsIBM·Filed 2004·Granted Aug 22, 2006·111 cites·52 claims
- 0697US6444592B1Interfacial oxidation process for high-k gate dielectric process integrationIBM·Filed 2000·Granted Sep 3, 2002·191 cites·22 claims
- 0793US5316615ASurfactant-enhanced epitaxyIBM·Filed 1993·Granted May 31, 1994·92 cites·12 claims
- 0892US10256405B2Methods for fabricating artificial neural networks (ANN) based on doped semiconductor elementsIBM·Filed 2017·Granted Apr 9, 2019·5 cites·20 claims
- 0992US7598545B2Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devicesIBM·Filed 2005·Granted Oct 6, 2009·20 cites·28 claims
- 1092US7452767B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high k dielectricsIBM·Filed 2006·Granted Nov 18, 2008·15 cites·4 claims
- 1192US7446380B2Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for CMOSIBM·Filed 2005·Granted Nov 4, 2008·20 cites·15 claims
- 1291US8193051B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectricsBOJARCZUK JR NESTOR A·Filed 2011·Granted Jun 5, 2012·14 cites·11 claims
- 1391US7928514B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectricsIBM·Filed 2009·Granted Apr 19, 2011·12 cites·16 claims
- 1491US6528374B2Method for forming dielectric stack without interfacial layerIBM·Filed 2001·Granted Mar 4, 2003·47 cites·20 claims
- 1590US7479683B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high-k dielectricsIBM·Filed 2004·Granted Jan 20, 2009·35 cites·17 claims
- 1690US5624869AMethod of forming a film for a multilayer Semiconductor device for improving thermal stability of cobalt silicide using platinum or nitrogenIBM·Filed 1994·Granted Apr 29, 1997·70 cites·40 claims
- 1789US7745278B2Selective implementation of barrier layers to achieve threshold voltage control in CMOS device fabrication with high K dielectricsIBM·Filed 2008·Granted Jun 29, 2010·10 cites·22 claims
- 1888US9263664B1Integrating a piezoresistive element in a piezoelectronic transistorIBM·Filed 2014·Granted Feb 16, 2016·5 cites·12 claims
- 1988US8803141B2Hydrazine-free solution deposition of chalcogenide filmsMITZI DAVID B·Filed 2011·Granted Aug 12, 2014·2 cites·8 claims
- 2088US8134150B2Hydrazine-free solution deposition of chalcogenide filmsMITZI DAVID B·Filed 2009·Granted Mar 13, 2012·5 cites·20 claims
- 2188US7858500B2Low threshold voltage semiconductor device with dual threshold voltage control meansIBM·Filed 2008·Granted Dec 28, 2010·12 cites·20 claims
- 2285US11882770B2Area-selective deposition of metal nitride to fabricate devicesIBM·Filed 2020·Granted Jan 23, 2024·1 cites·20 claims
- 2385US9472368B2Piezoelectronic switch device for RF applicationsIBM·Filed 2014·Granted Oct 18, 2016·4 cites·16 claims
- 2485US5608266AThin film for a multilayer semiconductor device for improving thermal stability and a method thereofIBM·Filed 1995·Granted Mar 4, 1997·58 cites·13 claims
- 2584US6566281B1Nitrogen-rich barrier layer and structures formedIBM·Filed 1997·Granted May 20, 2003·60 cites·27 claims
- 2684US6245616B1Method of forming oxynitride gate dielectricIBM·Filed 1999·Granted Jun 12, 2001·50 cites·11 claims
- 2783US8053772B2Hydrazine-free solution deposition of chalcogenide filmsIBM·Filed 2009·Granted Nov 8, 2011·2 cites·18 claims
- 2882US10269580B2Wet etching of samarium selenium for piezoelectric processingIBM·Filed 2017·Granted Apr 23, 2019·2 cites·11 claims
- 2982US9419201B2Integrating a piezoresistive element in a piezoelectronic transistorIBM·Filed 2015·Granted Aug 16, 2016·3 cites·8 claims
- 3081US10332753B2Wet etching of samarium selenium for piezoelectric processingIBM·Filed 2017·Granted Jun 25, 2019·2 cites·9 claims
- 3181US9419203B2Passivation and alignment of piezoelectronic transistor piezoresistorIBM·Filed 2015·Granted Aug 16, 2016·3 cites·12 claims
- 3281US9293687B1Passivation and alignment of piezoelectronic transistor piezoresistorIBM·Filed 2014·Granted Mar 22, 2016·3 cites·8 claims
- 3381US7999323B2Using metal/metal nitride bilayers as gate electrodes in self-aligned aggressively scaled CMOS devicesIBM·Filed 2009·Granted Aug 16, 2011·7 cites·18 claims
- 3481US6756646B2Oxynitride gate dielectric and method of formingIBM·Filed 2001·Granted Jun 29, 2004·24 cites·9 claims
- 3579US10170702B2Intermetallic contact for carbon nanotube FETsIBM·Filed 2017·Granted Jan 1, 2019·2 cites·16 claims
- 3679US7348226B2Method of forming lattice-matched structure on silicon and structure formed therebyIBM·Filed 2005·Granted Mar 25, 2008·5 cites·30 claims
- 3778US10748059B2Architecture for an electrochemical artificial neural networkIBM·Filed 2017·Granted Aug 18, 2020·3 cites·11 claims
- 3878US6735556B2Real-time model evaluationIBM·Filed 2001·Granted May 11, 2004·24 cites·18 claims
- 3974US5997638ALocalized lattice-mismatch-accomodation dislocation network epitaxyIBM·Filed 1995·Granted Dec 7, 1999·39 cites·12 claims
- 4073US7943458B2Methods for obtaining gate stacks with tunable threshold voltage and scalingIBM·Filed 2009·Granted May 17, 2011·5 cites·17 claims
- 4172US7960726B2Hydrazine-free solution deposition of chalcogenide filmsIBM·Filed 2009·Granted Jun 14, 2011·0 cites·20 claims
- 4271US7999255B2Hydrazine-free solution deposition of chalcogenide filmsIBM·Filed 2009·Granted Aug 16, 2011·0 cites·20 claims
- 4370US6933566B2Method of forming lattice-matched structure on silicon and structure formed therebyIBM·Filed 2002·Granted Aug 23, 2005·10 cites·31 claims
- 4468US10901010B2Measuring flux, current, or integrated charge of low energy particlesIBM·Filed 2019·Granted Jan 26, 2021·0 cites·20 claims
- 4566US5628834ASurfactant-enhanced epitaxyIBM·Filed 1995·Granted May 13, 1997·19 cites·10 claims
- 4664US11227996B2Artificial neural networks (ANN) including a resistive element based on doped semiconductor elementsIBM·Filed 2019·Granted Jan 18, 2022·0 cites·2 claims
- 4764US11024803B2Methods for fabricating artificial neural networks (ANN) based on doped semiconductor resistive random access memory (RRAM) elementsIBM·Filed 2019·Granted Jun 1, 2021·0 cites·19 claims
- 4864US11011387B2Wet etching of samarium selenium for piezoelectric processingIBM·Filed 2019·Granted May 18, 2021·0 cites·18 claims
- 4964US10930519B2Wet etching of samarium selenium for piezoelectric processingIBM·Filed 2019·Granted Feb 23, 2021·0 cites·20 claims
- 5061US10416199B2Measuring flux, current, or integrated charge of low energy particlesIBM·Filed 2017·Granted Sep 17, 2019·0 cites·18 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →