Inventor · disambiguated record
Andrew L. Hawkins
Also filed as: HAWKINS ANDREW L
34 granted patents·517 citations·filing 1995–2001
98Inventor score
Top patents by PatentIndex Score
34 records- 0188US5768196AShift-register based row select circuit with redundancy for a FIFO memoryCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jun 16, 1998·74 cites·18 claims
- 0284US6005796ASingle ended simpler dual port memory cellCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Dec 21, 1999·50 cites·21 claims
- 0379US6731566B1Single ended simplex dual port memory cellCYPRESS SEMICONDUCTOR CORP·Filed 2001·Granted May 4, 2004·28 cites·14 claims
- 0474US5642318ATesting method for FIFOSCYPRESS SEMICONDCUTOR CORP·Filed 1995·Granted Jun 24, 1997·46 cites·16 claims
- 0572US6262912B1Single ended simplex dual port memory cellCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jul 17, 2001·26 cites·17 claims
- 0670US6005795ASingle ended dual port memory cellCYPRESS SEMICONDUTOR CORP·Filed 1997·Granted Dec 21, 1999·26 cites·22 claims
- 0764US6078637AAddress counter test mode for memory deviceCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Jun 20, 2000·22 cites·16 claims
- 0862US5828624ADecoder circuit and method for disabling a number of columns or rows in a memoryCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Oct 27, 1998·20 cites·20 claims
- 0958US5862092ARead bitline writer for fallthru in fifosCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Jan 19, 1999·15 cites·20 claims
- 1056US6181595B1Single ended dual port memory cellCYPRESS SEMICONDUCTOR CORP·Filed 1999·Granted Jan 30, 2001·13 cites·2 claims
- 1155US6813741B1Address counter test mode for memory deviceCYPRESS SEMICONDUCTOR CORP·Filed 2000·Granted Nov 2, 2004·8 cites·21 claims
- 1251US5712992AState machine design for generating empty and full flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Jan 27, 1998·21 cites·20 claims
- 1349US5627797AFull and empty flag generator for synchronous FIFOSCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted May 6, 1997·21 cites·20 claims
- 1448US5852748AProgrammable read-write word line equality signal generation for FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Dec 22, 1998·20 cites·13 claims
- 1546US5850568ACircuit having plurality of carry/sum adders having read count, write count, and offset inputs to generate an output flag in response to FIFO fullnessCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Dec 15, 1998·16 cites·17 claims
- 1643US5936894ADual level wordline clamp for reduced memory cell currentCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Aug 10, 1999·7 cites·20 claims
- 1743US5751644AData transition detect write controlCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted May 12, 1998·9 cites·20 claims
- 1841US6070203ACircuit for generating almost full and almost empty flags in response to sum and carry outputs in asynchronous and synchronous FIFOSCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted May 30, 2000·10 cites·16 claims
- 1941US5809339AState machine design for generating half-full and half-empty flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Sep 15, 1998·11 cites·20 claims
- 2039US6023435AStaggered bitline precharge schemeCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Feb 8, 2000·6 cites·20 claims
- 2138US5661418ASignal generation decoder circuit and methodCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Aug 26, 1997·8 cites·24 claims
- 2236US5963056AFull and empty flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Oct 5, 1999·7 cites·40 claims
- 2336US5880997ABubbleback for FIFOSCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Mar 9, 1999·5 cites·11 claims
- 2436US5864507ADual level wordline clamp for reduced memory cell currentCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 26, 1999·4 cites·20 claims
- 2536US5673234ARead bitline writer for fallthru in FIFO'sCYPRESS SEMICONDUCTOR CORP·Filed 1995·Granted Sep 30, 1997·4 cites·9 claims
- 2635US5955897ASignal generation decoder circuit and methodCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Sep 21, 1999·6 cites·23 claims
- 2734US5994920AHalf-full flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Nov 30, 1999·5 cites·33 claims
- 2834US5991834AState machine design for generating half-full and half-empty flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Nov 23, 1999·5 cites·25 claims
- 2934US5860160AHigh speed FIFO mark and retransmit scheme using latches and prechargeCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 12, 1999·7 cites·20 claims
- 3033US6510486B1Clocking scheme for independently reading and writing multiple width words from a memory arrayCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 21, 2003·5 cites·15 claims
- 3133US6016403AState machine design for generating empty and full flags in an asynchronous FIFOCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Jan 18, 2000·4 cites·37 claims
- 3233US5844423AHalf-full flag generator for synchronous FIFOsCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Dec 1, 1998·4 cites·20 claims
- 3332US5860118ASRAM write partitioningCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 12, 1999·2 cites·16 claims
- 3431US6055177AMemory cellCYPRESS SEMICONDUCTOR CORP·Filed 1998·Granted Apr 25, 2000·2 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →