Inventor · disambiguated record
Tiao-Yuan Huang
Also filed as: HUANG TIAO-YUAN
35 granted patents·1,501 citations·filing 1987–2016
98Inventor score
Files withVLSI TECHNOLOGY INC12XEROX CORP8NAT SCIENCE COUNCIL7TAIWAN SEMICONDUCTOR MFG CO LTD2LIN HONG-NIEN1
Top patents by PatentIndex Score
35 records- 0198US5893741AMethod for simultaneously forming local interconnect with silicided elevated source/drain MOSFET'sNAT SCIENCE COUNCIL·Filed 1997·Granted Apr 13, 1999·428 cites·7 claims
- 0297US4907048ADouble implanted LDD transistor self-aligned with gateXEROX CORP·Filed 1987·Granted Mar 6, 1990·168 cites·11 claims
- 0395US4963504AMethod for fabricating double implanted LDD transistor self-aligned with gateXEROX CORP·Filed 1989·Granted Oct 16, 1990·115 cites·15 claims
- 0492US5783479AStructure and method for manufacturing improved FETs having T-shaped gatesNAT SCIENCE COUNCIL·Filed 1997·Granted Jul 21, 1998·103 cites·9 claims
- 0584US4951113ASimultaneously deposited thin film CMOS TFTs and their method of fabricationXEROX CORP·Filed 1988·Granted Aug 21, 1990·48 cites·3 claims
- 0683US5814544AForming a MOS transistor with a recessed channelVLSI TECHNOLOGY INC·Filed 1996·Granted Sep 29, 1998·59 cites·7 claims
- 0782US4904611AFormation of large grain polycrystalline filmsXEROX CORP·Filed 1988·Granted Feb 27, 1990·63 cites·18 claims
- 0881US9653552B2Body-tied, strained-channel multi-gate device and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 0981US9406800B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 2, 2016·2 cites·20 claims
- 1079US9214554B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Dec 15, 2015·2 cites·20 claims
- 1177US5618740AMethod of making CMOS output buffer with enhanced ESD resistanceVLSI TECHNOLOGY INC·Filed 1996·Granted Apr 8, 1997·36 cites·5 claims
- 1277US5517049ACMOS output buffer with enhanced ESD resistanceVLSI TECHNOLOGY INC·Filed 1994·Granted May 14, 1996·36 cites·5 claims
- 1376US4988638AMethod of fabrication a thin film SOI CMOS deviceXEROX CORP·Filed 1990·Granted Jan 29, 1991·40 cites·2 claims
- 1476US4945067AIntra-gate offset high voltage thin film transistor with misalignment immunity and method of its fabricationXEROX CORP·Filed 1989·Granted Jul 31, 1990·32 cites·3 claims
- 1575US6087189ATest structure for monitoring overetching of silicide during contact openingNAT SCIENCE COUNCIL·Filed 1997·Granted Jul 11, 2000·46 cites·3 claims
- 1673US6894352B2Single-electron transistor and fabrication method thereofFiled 2003·Granted May 17, 2005·20 cites·4 claims
- 1773US6432786B2Method of forming a gate oxide layer with an improved ability to resist the process damageNAT SCIENCE COUNCIL·Filed 2001·Granted Aug 13, 2002·16 cites·11 claims
- 1871US6667508B2Nonvolatile memory having a split gateFiled 2001·Granted Dec 23, 2003·17 cites·6 claims
- 1971US5394358ASRAM memory cell with tri-level local interconnectVLSI TECHNOLOGY INC·Filed 1994·Granted Feb 28, 1995·33 cites·4 claims
- 2070US4907041AIntra-gate offset high voltage thin film transistor with misalignment immunityXEROX CORP·Filed 1988·Granted Mar 6, 1990·26 cites·6 claims
- 2169US5038184AThin film varactorsXEROX CORP·Filed 1989·Granted Aug 6, 1991·27 cites·17 claims
- 2267US5413969ADifferential treatment to selectively avoid silicide formation on ESD I/O transistors in a salicide processVLSI TECHNOLOGY INC·Filed 1993·Granted May 9, 1995·26 cites·21 claims
- 2362US5529941AMethod for making an integrated circuit structureVLSI TECHNOLOGY INC·Filed 1994·Granted Jun 25, 1996·22 cites·22 claims
- 2461US5827768AMethod for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structureNAT SCIENCE COUNCIL·Filed 1997·Granted Oct 27, 1998·25 cites·4 claims
- 2560US8946811B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameLIN HONG-NIEN·Filed 2006·Granted Feb 3, 2015·2 cites·20 claims
- 2660US5418391ASemiconductor-on-insulator integrated circuit with selectively thinned channel regionVLSI TECHNOLOGY INC·Filed 1994·Granted May 23, 1995·20 cites·4 claims
- 2753US5581105ACMOS input buffer with NMOS gate coupled to VSS through undoped gate poly resistorVLSI TECHNOLOGY INC·Filed 1994·Granted Dec 3, 1996·13 cites·3 claims
- 2853US5510728AMulti-finger input buffer with transistor gates capacitively coupled to groundVLSI TECHNOLOGY INC·Filed 1995·Granted Apr 23, 1996·14 cites·3 claims
- 2953US5342798AMethod for selective salicidation of source/drain regions of a transistorVLSI TECHNOLOGY INC·Filed 1993·Granted Aug 30, 1994·23 cites·20 claims
- 3052US5998246ASelf-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drainNAT SCIENCE COUNCIL REPUBLIC CHINA·Filed 1997·Granted Dec 7, 1999·14 cites·10 claims
- 3150US5386134AAsymmetric electro-static discharge transistors for increased electro-static discharge hardnessVLSI TECHNOLOGY INC·Filed 1993·Granted Jan 31, 1995·13 cites·15 claims
- 3249US6495432B2Method of improving a dual gate CMOS transistor to resist the boron-penetrating effectNAT SCIENCE COUNCIL·Filed 2001·Granted Dec 17, 2002·2 cites·12 claims
- 3346US6555424B2Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the sameS M SZE·Filed 2001·Granted Apr 29, 2003·4 cites·9 claims
- 3434US5716860ACMOS input buffer with NMOS gate coupled to Vss through undoped gate poly resistorVLSI TECHNOLOGY INC·Filed 1996·Granted Feb 10, 1998·3 cites·2 claims
- 3531US6232206B1Method for forming electrostatic discharge (ESD) protection transistorsNAT SCIENCE COUNCIL·Filed 1998·Granted May 15, 2001·1 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →