Inventor · disambiguated record
Horng-Chih Lin
Also filed as: LIN HORNG-CHIH
21 granted patents·445 citations·filing 1995–2020
95Inventor score
Files withNAT SCIENCE COUNCIL7UNIV NAT CHIAO TUNG3IND TECH RES INST2NAT SCIENCE COUNCIL REPUBLIC CHINA2TAIWAN SEMICONDUCTOR MFG CO LTD2
Top patents by PatentIndex Score
21 records- 0193US5658806AMethod for fabricating thin-film transistor with bottom-gate or dual-gate configurationNAT SCIENCE COUNCIL·Filed 1995·Granted Aug 19, 1997·164 cites·20 claims
- 0292US5783479AStructure and method for manufacturing improved FETs having T-shaped gatesNAT SCIENCE COUNCIL·Filed 1997·Granted Jul 21, 1998·103 cites·9 claims
- 0390US7723789B2Nonvolatile memory device with nanowire channel and method for fabricating the sameUNIV NAT CHIAO TUNG·Filed 2008·Granted May 25, 2010·66 cites·13 claims
- 0481US9653552B2Body-tied, strained-channel multi-gate device and methodsTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2016·Granted May 16, 2017·2 cites·20 claims
- 0581US9406800B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameTAIWAN SEMICONDUCTOR MFG CO LTD·Filed 2015·Granted Aug 2, 2016·2 cites·20 claims
- 0679US9214554B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameTAIWAN SEMICONDUCTOR MFG·Filed 2015·Granted Dec 15, 2015·2 cites·20 claims
- 0773US6432786B2Method of forming a gate oxide layer with an improved ability to resist the process damageNAT SCIENCE COUNCIL·Filed 2001·Granted Aug 13, 2002·16 cites·11 claims
- 0871US6667508B2Nonvolatile memory having a split gateFiled 2001·Granted Dec 23, 2003·17 cites·6 claims
- 0965US8932916B2Method for fabricating thin-film transistorUNIV NAT CHIAO TUNG·Filed 2013·Granted Jan 13, 2015·3 cites·16 claims
- 1064US7504694B2Structure of semiconductor deviceIND TECH RES INST·Filed 2006·Granted Mar 17, 2009·2 cites·8 claims
- 1161US5827768AMethod for manufacturing an MOS transistor having a self-aligned and planarized raised source/drain structureNAT SCIENCE COUNCIL·Filed 1997·Granted Oct 27, 1998·25 cites·4 claims
- 1260US8946811B2Body-tied, strained-channel multi-gate device and methods of manufacturing sameLIN HONG-NIEN·Filed 2006·Granted Feb 3, 2015·2 cites·20 claims
- 1355US11257845B2Radio frequency integrated circuit having relatively small circuit area and method of fabricating the sameUNIV NATIONAL CHIAO TUNG·Filed 2020·Granted Feb 22, 2022·0 cites·10 claims
- 1452US7972912B2Method of fabricating semiconductor deviceIND TECH RES INST·Filed 2009·Granted Jul 5, 2011·0 cites·8 claims
- 1552US5998246ASelf-aligned manufacturing method of a thin film transistor for forming a single-crystal bottom-gate and an offset drainNAT SCIENCE COUNCIL REPUBLIC CHINA·Filed 1997·Granted Dec 7, 1999·14 cites·10 claims
- 1650US5714398ASelf-aligned tungsten strapped source/drain and gate technology for deep submicron CMOSNAT SCIENCE COUNCIL REPUBLIC CHINA·Filed 1996·Granted Feb 3, 1998·13 cites·1 claims
- 1749US7977755B2Suspended nanochannel transistor structure and method for fabricating the sameUNIV NAT CHIAO TUNG·Filed 2008·Granted Jul 12, 2011·1 cites·10 claims
- 1849US6495432B2Method of improving a dual gate CMOS transistor to resist the boron-penetrating effectNAT SCIENCE COUNCIL·Filed 2001·Granted Dec 17, 2002·2 cites·12 claims
- 1946US6555424B2Thin film transistor with sub-gates and schottky source/drain and a manufacturing method of the sameS M SZE·Filed 2001·Granted Apr 29, 2003·4 cites·9 claims
- 2031US6232206B1Method for forming electrostatic discharge (ESD) protection transistorsNAT SCIENCE COUNCIL·Filed 1998·Granted May 15, 2001·1 cites·11 claims
- 2130US5913123AManufacturing method for deep-submicron P-type metal-oxide semiconductor shallow junctionNAT SCIENCE COUNCIL·Filed 1997·Granted Jun 15, 1999·6 cites·8 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →