Inventor · disambiguated record
Mahesh Gopalan
Also filed as: GOPALAN MAHESH
18 granted patents·5 pending applications·74 citations·filing 2003–2024
93Inventor score
Top patents by PatentIndex Score
23 records- 0195US10032502B1Method for calibrating capturing read data in a read data path for a DDR memory interface circuitUNIQUIFY IP COMPANY LLC·Filed 2018·Granted Jul 24, 2018·13 cites·30 claims
- 0294US12014767B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY INC·Filed 2023·Granted Jun 18, 2024·1 cites·20 claims
- 0392US10229729B2Method for calibrating capturing read data in a read data path for a DDR memory interface circuitUNIQUIFY INC·Filed 2017·Granted Mar 12, 2019·5 cites·135 claims
- 0490US7975164B2DDR memory controllerUNIQUIFY INC·Filed 2008·Granted Jul 5, 2011·28 cites·9 claims
- 0589US10586585B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY IP COMPANY LLC·Filed 2019·Granted Mar 10, 2020·4 cites·70 claims
- 0688US9805784B2Multiple gating modes and half-frequency dynamic calibration for DDR memory controllersUNIQUIFY INC·Filed 2016·Granted Oct 31, 2017·3 cites·16 claims
- 0785US2024290372A1Double data rate (ddr) memory controller apparatus and methodUNIQUIFY INC·Filed 2024·Application pending·0 cites
- 0882US10734061B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY IP COMPANY LLC·Filed 2019·Granted Aug 4, 2020·2 cites·44 claims
- 0977US11710516B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY INC·Filed 2022·Granted Jul 25, 2023·0 cites·20 claims
- 1077US9431091B2Multiple gating modes and half-frequency dynamic calibration for DDR memory controllersUNIQUIFY INC·Filed 2015·Granted Aug 30, 2016·1 cites·16 claims
- 1173US10269408B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY IP COMPANY LLC·Filed 2018·Granted Apr 23, 2019·1 cites·30 claims
- 1272US11348632B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY INC·Filed 2020·Granted May 31, 2022·0 cites·104 claims
- 1364US7320013B2Method and apparatus for aligning operands for a processorADAPTEC INC·Filed 2003·Granted Jan 15, 2008·12 cites·18 claims
- 1459US8661356B2Time application having an intergrated check engineDEMANT HILMAR·Filed 2010·Granted Feb 25, 2014·2 cites·20 claims
- 1559US2023316145A1Systems and methods for knowledge extractionXFORMICS INC·Filed 2023·Application pending·0 cites
- 1656US10242730B2Double data rate (DDR) memory controller apparatus and methodUNIQUIFY IP COMPANY LLC·Filed 2018·Granted Mar 26, 2019·0 cites·30 claims
- 1755US9300443B2Methods for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handlingUNIQUIFY INC·Filed 2014·Granted Mar 29, 2016·0 cites·10 claims
- 1853US2014281662A1Dynamically adaptive bit-leveling for data interfacesUNIQUIFY INC·Filed 2013·Application pending·0 cites
- 1952US7571258B2Method and apparatus for a pipeline architectureADAPTEC INC·Filed 2003·Granted Aug 4, 2009·2 cites·19 claims
- 2051US9584309B2Circuit for dynamically adaptive bit-leveling by incremental sampling, jitter detection, and exception handlingUNIQUIFY INC·Filed 2016·Granted Feb 28, 2017·0 cites·12 claims
- 2141US7877581B2Networked processor for a pipeline architecturePMC SIERRA US INC·Filed 2003·Granted Jan 25, 2011·0 cites·19 claims
- 2241US2012060141A1Integrated environment for software design and implementationDEMANT HILMAR·Filed 2010·Application pending·0 cites
- 2328US2012030612A1Dynamic property attributesAZIZ ABDUL·Filed 2010·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Mahesh Gopalan files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →