Inventor · disambiguated record
Ding-Ming Kwai
Also filed as: KWAI DING-MING
26 granted patents·5 pending applications·127 citations·filing 1999–2017
95Inventor score
Top patents by PatentIndex Score
31 records- 0193US8710676B2Stacked structure and stacked method for three-dimensional chipCHOU YUNG-FA·Filed 2011·Granted Apr 29, 2014·19 cites·14 claims
- 0281US9406401B23-D memory and built-in self-test circuit thereofIND TECH RES INST·Filed 2012·Granted Aug 2, 2016·10 cites·11 claims
- 0381US8689160B2Method and apparatus of an integrated circuitIND TECH RES INST·Filed 2013·Granted Apr 1, 2014·6 cites·11 claims
- 0480US8531199B2Method for testing through-silicon-via and the circuit thereofWU CHENG WEN·Filed 2010·Granted Sep 10, 2013·4 cites·5 claims
- 0577US8384201B2Wafer and method for improving yield rate of waferIND TECH RES INST·Filed 2009·Granted Feb 26, 2013·5 cites·18 claims
- 0676US10564706B2Power source tolerance analysis method and systemIND TECH RES INST·Filed 2016·Granted Feb 18, 2020·3 cites·13 claims
- 0776US10289141B2Method for generating power distribution network (PDN) model, and power distribution network analysis method and deviceIND TECH RES INST·Filed 2015·Granted May 14, 2019·3 cites·9 claims
- 0876US9183345B2Apparatus and method for generating a power delivery networkIND TECH RES INST·Filed 2014·Granted Nov 10, 2015·5 cites·22 claims
- 0976US8522186B2Method and apparatus of an integrated circuitLIN CHANG TZU·Filed 2011·Granted Aug 27, 2013·6 cites·16 claims
- 1075US8193006B2Method of chip repair by stacking a plurality of bad diesCHOU YUNG-FA·Filed 2009·Granted Jun 5, 2012·6 cites·9 claims
- 1171US6351837B1High speed built-in self-test circuit for DRAMSTAIWAN SEMICONDUCTOR MFG CORP·Filed 1999·Granted Feb 26, 2002·32 cites·7 claims
- 1269US9588717B2Fault-tolerance through silicon via interface and controlling method thereofIND TECH RES INST·Filed 2014·Granted Mar 7, 2017·3 cites·16 claims
- 1367US9064549B2Memory deviceIND TECH RES INST·Filed 2014·Granted Jun 23, 2015·3 cites·27 claims
- 1467US7924083B2Isolation circuitIND TECH RES INST·Filed 2009·Granted Apr 12, 2011·5 cites·21 claims
- 1565US8854853B2Technology of memory repair after stacking of three-dimensional integrated circuitCHOU YUNG-FA·Filed 2011·Granted Oct 7, 2014·3 cites·14 claims
- 1664US8217521B2Hardwired switch of die stack and operating method of hardwired switchCHEN TING-SHENG·Filed 2009·Granted Jul 10, 2012·2 cites·13 claims
- 1762US8683276B2Apparatus and method for repairing an integrated circuitCHOU YUNG-FA·Filed 2012·Granted Mar 25, 2014·1 cites·26 claims
- 1862US8344520B2Stacked structure of chipsIND TECH RES INST·Filed 2012·Granted Jan 1, 2013·1 cites·9 claims
- 1955US8937486B2Method for testing through-silicon-viaNAT UNIV TSING HUA·Filed 2013·Granted Jan 20, 2015·0 cites·7 claims
- 2049US2011080184A1Method for testing through-silicon-via and the circuit thereofNAT UNIV TSING HUA·Filed 2009·Application pending·0 cites
- 2147US8026585B2Die stacking structure and fabricating method thereofIND TECH RES INST·Filed 2009·Granted Sep 27, 2011·0 cites·16 claims
- 2245US8912015B2Operating method of hardwired switchCHEN TING-SHENG·Filed 2012·Granted Dec 16, 2014·0 cites·6 claims
- 2345US6647524B1Built-in-self-test circuit for RAMBUS direct RDRAMWORLDWIDE SEMICONDUCTOR MFG·Filed 1999·Granted Nov 11, 2003·10 cites·4 claims
- 2444US9347981B2Test method for interposerIND TECH RES INST·Filed 2013·Granted May 24, 2016·0 cites·13 claims
- 2542US2014325311A1Hybrid error correction method and memory repair apparatus thereofIND TECH RES INST·Filed 2013·Application pending·0 cites
- 2638US2011304010A1Electrostatic discharge protection scheme for semiconductor device stacking processJIANG ZHE-WEI·Filed 2010·Application pending·0 cites
- 2737US9905277B2Memory controlling method and memory systemIND TECH RES INST·Filed 2015·Granted Feb 27, 2018·0 cites·18 claims
- 2835US2012133807A1Image capture deviceWU CHENG-WEN·Filed 2010·Application pending·0 cites
- 2934US9048342B2Semiconductor device stacked structureKWAI DING-MING·Filed 2012·Granted Jun 2, 2015·0 cites·21 claims
- 3034US2007133275A1Low-power reading reference circuit for split-gate flash memoryINTELLECTUAL PROPERTY LIBARARY·Filed 2006·Application pending·0 cites
- 3132US10339253B2Method of yield prejudgment and bump re-assignment and computer readable storage mediumIND TECH RES INST·Filed 2017·Granted Jul 2, 2019·0 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →