Inventor · disambiguated record
Thomas J. Krutsick
Also filed as: KRUTSICK THOMAS · KRUTSICK THOMAS J · KRUTSICK THOMAS JOSEPH
19 granted patents·7 pending applications·182 citations·filing 1999–2024
94Inventor score
Files withAGERE SYSTEMS INC10ZARLINK SEMICONDUCTOR US INC6AGERE SYST GUARDIAN CORP4KRUTSICK THOMAS J2KRUTSICK THOMAS JOSEPH2
Top patents by PatentIndex Score
26 records- 0184US6066884ASchottky diode guard ring structuresLUCENT TECHNOLOGIES INC·Filed 1999·Granted May 23, 2000·61 cites·4 claims
- 0277US6399413B1Self aligned gated Schottky diode guard ring structuresAGERE SYST GUARDIAN CORP·Filed 2000·Granted Jun 4, 2002·27 cites·5 claims
- 0374US8542848B1Musical instrument preamplifierKRUTSICK THOMAS JOSEPH·Filed 2008·Granted Sep 24, 2013·11 cites·1 claims
- 0473US7821016B2Light activated silicon controlled switchZARLINK SEMICONDUCTOR US INC·Filed 2008·Granted Oct 26, 2010·2 cites·10 claims
- 0573US6767797B2Method of fabricating complementary self-aligned bipolar transistorsAGERE SYSTEMS INC·Filed 2002·Granted Jul 27, 2004·20 cites·13 claims
- 0672US7715162B2Optically triggered electro-static discharge protection circuitZARLINK SEMICONDUCTOR US INC·Filed 2008·Granted May 11, 2010·5 cites·17 claims
- 0771US7605010B1Integrated silicon optical isolatorZARLINK SEMICONDUCTOR US INC·Filed 2008·Granted Oct 20, 2009·4 cites·18 claims
- 0870US6727567B2Integrated circuit device substrates with selective epitaxial growth thickness compensationAGERE SYSTEMS INC·Filed 2002·Granted Apr 27, 2004·16 cites·5 claims
- 0967US8269265B2Trench capacitor for high voltage processes and method of manufacturing the sameKRUTSICK THOMAS J·Filed 2008·Granted Sep 18, 2012·5 cites·19 claims
- 1063US6790753B2Field plated schottky diode and method of fabrication thereforAGERE SYSTEMS INC·Filed 2003·Granted Sep 14, 2004·10 cites·15 claims
- 1162US8012775B2Method of forming a light activated silicon controlled switchZARLINK SEMICONDUCTOR US INC·Filed 2010·Granted Sep 6, 2011·0 cites·10 claims
- 1257US2025112035A1Hybrid semiconductor wafer and method of formingMICROCHIP TECH INC·Filed 2024·Application pending·0 cites
- 1354US6690037B1Field plated Schottky diodeAGERE SYSTEMS INC·Filed 2000·Granted Feb 10, 2004·6 cites·16 claims
- 1449US6828649B2Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture thereforAGERE SYSTEMS INC·Filed 2002·Granted Dec 7, 2004·4 cites·17 claims
- 1547US6555852B1Bipolar transistor having an emitter comprised of a semi-insulating materialAGERE SYSTEMS INC·Filed 2002·Granted Apr 29, 2003·3 cites·13 claims
- 1641US7439146B1Field plated resistor with enhanced routing area thereoverAGERE SYSTEMS INC·Filed 2000·Granted Oct 21, 2008·1 cites·6 claims
- 1741US6737311B2Semiconductor device having a buried layer for reducing latchup and a method of manufacture thereforAGERE SYSTEMS INC·Filed 2001·Granted May 18, 2004·1 cites·17 claims
- 1841US6458669B1Method of manufacturing an integrated circuitAGERE SYST GUARDIAN CORP·Filed 2000·Granted Oct 1, 2002·1 cites·10 claims
- 1940US2004251511A1Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture thereforAGERE SYSTEMS INC·Filed 2004·Application pending·0 cites
- 2038US2010009507A1Method of constructing cmos device tubsKRUTSICK THOMAS J·Filed 2008·Application pending·0 cites
- 2137US2003211701A1Semiconductor device including an isolation trench having a dopant barrier layer formed on a sidewall thereof and a method of manufacture thereforAGERE SYSTEMS INC·Filed 2002·Application pending·0 cites
- 2236US8035196B2Methods of counter-doping collector regions in bipolar transistorsZARLINK SEMICONDUCTOR US INC·Filed 2008·Granted Oct 11, 2011·0 cites·16 claims
- 2336US2009250785A1Methods of forming a shallow base region of a bipolar transistorKRUTSICK THOMAS JOSEPH·Filed 2008·Application pending·0 cites
- 2436US2011143513A1Methods of forming a shallow base region of a bipolar transistorZARLINK SEMICONDUCTOR US INC·Filed 2011·Application pending·0 cites
- 2534US6409829B1Manufacture of dielectrically isolated integrated circuitsAGERE SYST GUARDIAN CORP·Filed 1999·Granted Jun 25, 2002·5 cites·4 claims
- 2632US2003141566A1Method of simultaneously manufacturing a metal oxide semiconductor device and a bipolar deviceAGERE SYST GUARDIAN CORP·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →