Inventor · disambiguated record
Li-Chih Chao
Also filed as: CHAO LI-CHIH
20 granted patents·1,122 citations·filing 1997–2004
96Inventor score
Top patents by PatentIndex Score
20 records- 0198US6743732B1Organic low K dielectric etch with NH3 chemistryTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Jun 1, 2004·249 cites·7 claims
- 0297US6323121B1Fully dry post-via-etch cleaning method for a damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Nov 27, 2001·206 cites·22 claims
- 0394US6165880ADouble spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuitsTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Dec 26, 2000·186 cites·14 claims
- 0492US6720256B1Method of dual damascene patterningTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Apr 13, 2004·78 cites·43 claims
- 0590US6376366B1Partial hard mask open process for hard mask dual damascene etchTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Apr 23, 2002·49 cites·18 claims
- 0686US6211061B1Dual damascene process for carbon-based low-K materialsTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Apr 3, 2001·91 cites·14 claims
- 0785US6458650B1CU second electrode process with in situ ashing and oxidation processTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Oct 1, 2002·34 cites·23 claims
- 0877US6797630B1Partial via hard mask open on low-k dual damascene etch with dual hard mask (DHM) approachTAIWAN SEMICONDUCTOR MFG·Filed 2002·Granted Sep 28, 2004·20 cites·34 claims
- 0977US6495469B1High selectivity, low etch depth micro-loading process for non stop layer damascene etchTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Dec 17, 2002·20 cites·36 claims
- 1077US6457477B1Method of cleaning a copper/porous low-k dual damascene etchTAIWAN SEMICONDUCTOR MFG·Filed 2000·Granted Oct 1, 2002·31 cites·31 claims
- 1174US6063711AHigh selectivity etching stop layer for damascene processTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted May 16, 2000·47 cites·23 claims
- 1271US6551938B1N2/H2 chemistry for dry development in top surface imaging technologyTAIWON SEMICONDUCTOR MFG COMPA·Filed 2002·Granted Apr 22, 2003·17 cites·36 claims
- 1368US6429119B1Dual damascene process to reduce etch barrier thicknessTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Aug 6, 2002·36 cites·48 claims
- 1464US5872063ASelf-aligned contact structures using high selectivity etchingTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Feb 16, 1999·25 cites·14 claims
- 1551US7253112B2Dual damascene processTAIWAN SEMICONDUCTOR MFG·Filed 2004·Granted Aug 7, 2007·5 cites·20 claims
- 1650US6140218AMethod for fabricating a T-shaped hard mask/conductor profile to improve self-aligned contact isolationTAIWAN SEMICONDUCTOR MFG·Filed 1999·Granted Oct 31, 2000·12 cites·14 claims
- 1746US6727183B1Prevention of spiking in ultra low dielectric constant materialTAIWAN SEMICONDUCTOR MFG·Filed 2001·Granted Apr 27, 2004·2 cites·29 claims
- 1841US6172411B1Self-aligned contact structures using high selectivity etchingTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Jan 9, 2001·7 cites·6 claims
- 1937US6107206AMethod for etching shallow trenches in a semiconductor bodyTAIWAN SEMICONDUCTOR MFG·Filed 1998·Granted Aug 22, 2000·6 cites·20 claims
- 2031US6184149B1Method for monitoring self-aligned contact etchingTAIWAN SEMICONDUCTOR MFG·Filed 1997·Granted Feb 6, 2001·1 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →