Inventor · disambiguated record
Ashesh Parikh
Also filed as: PARIKH ASHESH
16 granted patents·4 pending applications·62 citations·filing 2001–2020
91Inventor score
Top patents by PatentIndex Score
20 records- 0188US7772059B2Method for fabricating graphene transistors on a silicon or SOI substrateTEXAS INSTRUMENTS INC·Filed 2008·Granted Aug 10, 2010·17 cites·12 claims
- 0283US7687308B2Method for fabricating carbon nanotube transistors on a silicon or SOI substrateTEXAS INSTRUMENTS INC·Filed 2008·Granted Mar 30, 2010·19 cites·6 claims
- 0381US9496313B2CMOS-based thermopile with reduced thermal conductanceTEXAS INSTRUMENTS INC·Filed 2014·Granted Nov 15, 2016·4 cites·5 claims
- 0470US9853086B2CMOS-based thermopile with reduced thermal conductanceTEXAS INSTRUMENTS INC·Filed 2016·Granted Dec 26, 2017·1 cites·14 claims
- 0570US9665675B2Method to improve transistor matchingTEXAS INSTRUMENTS INC·Filed 2014·Granted May 30, 2017·2 cites·4 claims
- 0669US10339251B2Method to improve transistor matchingTEXAS INSTRUMENTS INC·Filed 2017·Granted Jul 2, 2019·1 cites·11 claims
- 0769US7985990B2Transistor layout for manufacturing process controlTEXAS INSTRUMENTS INC·Filed 2009·Granted Jul 26, 2011·3 cites·32 claims
- 0867US8394681B2Transistor layout for manufacturing process controlPARIKH ASHESH·Filed 2010·Granted Mar 12, 2013·3 cites·4 claims
- 0966US8806388B2Extraction of imaging parameters for computational lithography using a data weighting algorithmTEXAS INSTRUMENTS INC·Filed 2013·Granted Aug 12, 2014·1 cites·11 claims
- 1063US8793626B2Computational lithography with feature upsizingTEXAS INSTRUMENTS INC·Filed 2013·Granted Jul 29, 2014·1 cites·18 claims
- 1163US7562333B2Method and process for generating an optical proximity correction model based on layout densityTEXAS INSTRUMENTS INC·Filed 2004·Granted Jul 14, 2009·7 cites·16 claims
- 1261US7458058B2Verifying a process margin of a mask pattern using intermediate stage modelsTEXAS INSTRUMENTS INC·Filed 2005·Granted Nov 25, 2008·1 cites·18 claims
- 1358US7842955B2Carbon nanotube transistors on a silicon or SOI substrateTEXAS INSTRUMENTS INC·Filed 2010·Granted Nov 30, 2010·2 cites·14 claims
- 1442US2013254725A1Extraction of imaging parameters for computational lithography using a data weighting algorithmTEXAS INSTRUMENTS INC·Filed 2013·Application pending·0 cites
- 1539US8015513B2OPC models generated from 2D high frequency test patternsTEXAS INSTRUMENTS INC·Filed 2008·Granted Sep 6, 2011·0 cites·17 claims
- 1635US11775852B2Network optimizationACCENTURE GLOBAL SOLUTIONS LTD·Filed 2019·Granted Oct 3, 2023·0 cites·17 claims
- 1735US2012117519A1Method of transistor matchingPARIKH ASHESH·Filed 2011·Application pending·0 cites
- 1835US2012105046A1Current mirror using ambipolar devicesMARSHALL ANDREW·Filed 2010·Application pending·0 cites
- 1934US12020124B2Selecting optimum primary and secondary parameters to calibrate and generate an unbiased forecasting modelACCENTURE GLOBAL SOLUTIONS LTD·Filed 2020·Granted Jun 25, 2024·0 cites·20 claims
- 2030US2002086242A1Novel low defect developer rinse process for 0.15 micron cmos technologyFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →