Inventor · disambiguated record
Yoshihiro Takamatsuya
Also filed as: TAKAMATSUYA YOSHIHIRO
13 granted patents·1 pending application·293 citations·filing 1995–2011
93Inventor score
Top patents by PatentIndex Score
14 records- 0189US6154808AMethod and apparatus for controlling data erase operations of a non-volatile memory deviceFUJITSU LTD·Filed 1998·Granted Nov 28, 2000·82 cites·15 claims
- 0287US8446382B2Information processing apparatus and input control methodGOTO MASAYUKI·Filed 2010·Granted May 21, 2013·18 cites·4 claims
- 0384US6643730B2CPU controlled memory controlling device for accessing operational informationFUJITSU LTD·Filed 2001·Granted Nov 4, 2003·38 cites·8 claims
- 0484US5758228AImage forming apparatus, control method for controlling the same and temperature control apparatusFUJITSU LTD·Filed 1995·Granted May 26, 1998·33 cites·15 claims
- 0582US6018140AImage forming apparatus, control method for controlling the same and temperature control apparatusFUJITSU LTD·Filed 1998·Granted Jan 25, 2000·29 cites·3 claims
- 0676US7448069B2Access-request control method, driver program for communication device, and communication deviceFUJITSU LTD·Filed 2005·Granted Nov 4, 2008·7 cites·9 claims
- 0768US9000956B2Portable terminal and input control methodGOTO MASAYUKI·Filed 2011·Granted Apr 7, 2015·3 cites·12 claims
- 0868US7447976B2Data transfer apparatusFUJITSU LTD·Filed 2005·Granted Nov 4, 2008·4 cites·7 claims
- 0968US6418501B1Memory cardFUJITSU LTD·Filed 1999·Granted Jul 9, 2002·54 cites·8 claims
- 1064US7349407B1Protocol conversion apparatus, communication apparatus, communication program storage medium, and communication systemFUJITSU LTD·Filed 2000·Granted Mar 25, 2008·11 cites·6 claims
- 1148US6449681B1Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffersFUJITSU LTD·Filed 2001·Granted Sep 10, 2002·5 cites·6 claims
- 1243US2004267973A1Device and host machineFUJITSU LTD·Filed 2004·Application pending·0 cites
- 1335US6289411B1Circuit for generating a chip-enable signal for a multiple chip configurationFUJITSU LTD·Filed 1999·Granted Sep 11, 2001·7 cites·16 claims
- 1431US6339809B1Memory unit and buffer access control circuit for updating an address when consecutively accessing upper and lower buffersFUJITSU LTD·Filed 1999·Granted Jan 15, 2002·2 cites·2 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →