Inventor · disambiguated record
Khader S. Abdel-Hafez
Also filed as: ABDEL-HAFEZ KHADER · ABDEL-HAFEZ KHADER S
14 granted patents·2 pending applications·415 citations·filing 2003–2022
93Inventor score
Top patents by PatentIndex Score
16 records- 0196US7412672B1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Aug 12, 2008·36 cites·58 claims
- 0296US7058869B2Method and apparatus for debug, diagnosis, and yield improvement of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Jun 6, 2006·119 cites·34 claims
- 0395US7032148B2Mask network design for scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Apr 18, 2006·84 cites·76 claims
- 0490US7231570B2Method and apparatus for multi-level scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Jun 12, 2007·21 cites·30 claims
- 0587US7512851B2Method and apparatus for shifting at-speed scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Mar 31, 2009·39 cites·46 claims
- 0687US7210082B1Method for performing ATPG and fault simulation in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Apr 24, 2007·16 cites·10 claims
- 0786US7552373B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Jun 23, 2009·36 cites·44 claims
- 0884US7124342B2Smart capture for ATPG (automatic test pattern generation) and fault simulation of scan-based integrated circuitsSYNTEST TECHNOLOGIES INC·Filed 2004·Granted Oct 17, 2006·31 cites·102 claims
- 0983US7590905B2Method and apparatus for pipelined scan compressionSYNTEST TECHNOLOGIES INC·Filed 2005·Granted Sep 15, 2009·13 cites·40 claims
- 1078US7444567B2Method and apparatus for unifying self-test with scan-test during prototype debug and production testSYNTEST TECHNOLOGIES INC·Filed 2003·Granted Oct 28, 2008·17 cites·18 claims
- 1159US7721173B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2009·Granted May 18, 2010·3 cites·47 claims
- 1258US11493971B2Power estimation systemSYNOPSYS INC·Filed 2021·Granted Nov 8, 2022·0 cites·19 claims
- 1357US12320839B2Distributed test pattern generation and synchronizationSYNOPSYS INC·Filed 2022·Granted Jun 3, 2025·0 cites·20 claims
- 1453US9696377B2Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECH INC·Filed 2015·Granted Jul 4, 2017·0 cites·12 claims
- 1547US2008276141A1Method and apparatus for broadcasting scan patterns in a scan-based integrated circuitSYNTEST TECHNOLOGIES INC·Filed 2008·Application pending·0 cites
- 1635US2004153926A1Method and apparatus for testing asynchronous set/reset faults in a scan-based integrated circuitFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →