Inventor · disambiguated record
Satish B. Sivaswamy
Also filed as: SIVASWAMY SATISH · SIVASWAMY SATISH B
11 granted patents·1 pending application·38 citations·filing 2016–2023
86Inventor score
Files withXILINX INC12
Top patents by PatentIndex Score
12 records- 0196US11238206B1Partition wire assignment for routing multi-partition circuit designsXILINX INC·Filed 2021·Granted Feb 1, 2022·14 cites·20 claims
- 0293US11790139B1Predicting a performance metric based on features of a circuit design and explaining marginal contributions of the features to the predictionXILINX INC·Filed 2022·Granted Oct 17, 2023·5 cites·20 claims
- 0389US9842187B1Representation of complex timing characteristics of startpoint-endpoint pairs in a circuit designXILINX INC·Filed 2016·Granted Dec 12, 2017·9 cites·20 claims
- 0483US11875100B1Distributed parallel processing routingXILINX INC·Filed 2021·Granted Jan 16, 2024·2 cites·20 claims
- 0583US10318699B1Fixing hold time violations using hold time budgets and slacks of setup timesXILINX INC·Filed 2017·Granted Jun 11, 2019·4 cites·20 claims
- 0681US11709521B1Synchronous clock domain crossing skew optimization and multi-clock buffer (MBUFG)XILINX INC·Filed 2020·Granted Jul 25, 2023·2 cites·17 claims
- 0772US11108644B1Data processing engine (DPE) array routingXILINX INC·Filed 2019·Granted Aug 31, 2021·2 cites·20 claims
- 0856US12327077B2Deadlock detection and prevention for routing packet-switched nets in electronic systemsXILINX INC·Filed 2022·Granted Jun 10, 2025·0 cites·20 claims
- 0953US2025077757A1Low-skew solutions for local clock nets in integrated circuitsXILINX INC·Filed 2023·Application pending·0 cites
- 1049US11733980B2Application implementation and buffer allocation for a data processing engine arrayXILINX INC·Filed 2021·Granted Aug 22, 2023·0 cites·20 claims
- 1147US12019964B1Optimizing use of computer resources in implementing circuit designs through machine learningXILINX INC·Filed 2021·Granted Jun 25, 2024·0 cites·20 claims
- 1246US11604751B1Optimizing hardware design throughput by latency aware balancing of re-convergent pathsXILINX INC·Filed 2021·Granted Mar 14, 2023·0 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →