Inventor · disambiguated record
Ziyad Hanna
Also filed as: HANNA ZIYAD · HANNA ZIYAD E
17 granted patents·141 citations·filing 2000–2019
94Inventor score
Technology areasG06F
Files withINTEL CORP7CADENCE DESIGN SYSTEMS INC3JASPER DESIGN AUTOMATION INC3BEN-TZUR ASA1HANNA ZIYAD1
Top patents by PatentIndex Score
17 records- 0190US10789404B1System, method, and computer program product for generating a formal verification modelCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Sep 29, 2020·7 cites·20 claims
- 0289US8739092B1Functional property rankingBEN-TZUR ASA·Filed 2012·Granted May 27, 2014·23 cites·22 claims
- 0387US8863049B1Constraining traces in formal verificationLUNDGREN LARS·Filed 2010·Granted Oct 14, 2014·16 cites·18 claims
- 0482US10983758B1System, method, and computer program product for automatically inferring case-split hints in equivalence checking of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 20, 2021·3 cites·20 claims
- 0581US9158874B1Formal verification coverage metrics of covered events for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Oct 13, 2015·6 cites·20 claims
- 0679US8826201B1Formal verification coverage metrics for circuit design propertiesJASPER DESIGN AUTOMATION INC·Filed 2013·Granted Sep 2, 2014·5 cites·18 claims
- 0778US10984161B1System, method, and computer program product for sequential equivalence checking in formal verificationCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Apr 20, 2021·2 cites·17 claims
- 0876US6567959B2Method and device for verification of VLSI designsINTEL CORP·Filed 2001·Granted May 20, 2003·26 cites·29 claims
- 0969US9177089B2Formal verification coverage metrics for circuit design propertiesHANNA ZIYAD E·Filed 2014·Granted Nov 3, 2015·3 cites·20 claims
- 1067US9460252B1Functional property rankingJASPER DESIGN AUTOMATION INC·Filed 2014·Granted Oct 4, 2016·2 cites·22 claims
- 1164US9372949B1Guided exploration of circuit design statesHANNA ZIYAD·Filed 2011·Granted Jun 21, 2016·3 cites·20 claims
- 1261US6792581B2Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verificationINTEL CORP·Filed 2002·Granted Sep 14, 2004·9 cites·15 claims
- 1361US6564358B2Method and system for formal verification of a circuit model using binary decision diagramsINTEL CORP·Filed 2000·Granted May 13, 2003·12 cites·28 claims
- 1459US7730436B2Verification using simultaneous and inductive SAT algorithmsINTEL CORP·Filed 2006·Granted Jun 1, 2010·4 cites·17 claims
- 1557US7073141B2Device, system and method for VLSI design analysisINTEL CORP·Filed 2003·Granted Jul 4, 2006·12 cites·42 claims
- 1653US7159201B2Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verificationINTEL CORP·Filed 2004·Granted Jan 2, 2007·4 cites·18 claims
- 1752US7117465B2Application of the retimed normal form to the formal equivalence verification of abstract RTL descriptions for pipelined designsINTEL CORP·Filed 2003·Granted Oct 3, 2006·4 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →