Inventor · disambiguated record
William Francis Landers
Also filed as: LANDERS WILLIAM · LANDERS WILLIAM F · LANDERS WILLIAM FRANCIS
33 granted patents·8 pending applications·696 citations·filing 1995–2024
97Inventor score
Top patents by PatentIndex Score
41 records- 0197US11469485B2Embedded microstrip transmission lineIBM·Filed 2020·Granted Oct 11, 2022·5 cites·18 claims
- 0295US7312529B2Structure and method for producing multiple size interconnectionsIBM·Filed 2005·Granted Dec 25, 2007·36 cites·18 claims
- 0394US5676587ASelective polish process for titanium, titanium nitride, tantalum and tantalum nitrideIBM·Filed 1995·Granted Oct 14, 1997·231 cites·5 claims
- 0490US9059167B2Structure and method for making crack stop for 3D integrated circuitsIBM·Filed 2014·Granted Jun 16, 2015·8 cites·17 claims
- 0589US8859390B2Structure and method for making crack stop for 3D integrated circuitsFAROOQ MUKTA G·Filed 2010·Granted Oct 14, 2014·9 cites·10 claims
- 0689US7544602B2Method and structure for ultra narrow crack stop for multilevel semiconductor deviceIBM·Filed 2007·Granted Jun 9, 2009·18 cites·1 claims
- 0789US7098676B2Multi-functional structure for enhanced chip manufacturibility and reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitorIBM·Filed 2003·Granted Aug 29, 2006·49 cites·12 claims
- 0888US11458474B2Microfluidic chips with one or more viasIBM·Filed 2018·Granted Oct 4, 2022·3 cites·6 claims
- 0988US8691691B2TSV pillar as an interconnecting structureFAROOQ MUKTA G·Filed 2011·Granted Apr 8, 2014·10 cites·16 claims
- 1087US8546961B2Alignment marks to enable 3D integrationFAROOQ MUKTA G·Filed 2011·Granted Oct 1, 2013·9 cites·19 claims
- 1186US7714452B2Structure and method for producing multiple size interconnectionsIBM·Filed 2007·Granted May 11, 2010·15 cites·14 claims
- 1285US6650010B2Unique feature design enabling structural integrity for advanced low K semiconductor chipsIBM·Filed 2002·Granted Nov 18, 2003·42 cites·13 claims
- 1382US6221775B1Combined chemical mechanical polishing and reactive ion etching processIBM·Filed 1998·Granted Apr 24, 2001·64 cites·26 claims
- 1477US12166260B2Embedded microstrip transmission lineIBM·Filed 2022·Granted Dec 10, 2024·0 cites·20 claims
- 1577US7009280B2Low-k interlevel dielectric layer (ILD)IBM·Filed 2004·Granted Mar 7, 2006·15 cites·17 claims
- 1677US6325696B1Piezo-actuated CMP carrierIBM·Filed 1999·Granted Dec 4, 2001·50 cites·14 claims
- 1774US7863183B2Method for fabricating last level copper-to-C4 connection with interfacial cap structureIBM·Filed 2006·Granted Jan 4, 2011·6 cites·18 claims
- 1874US7294565B2Method of fabricating a wire bond pad with Ni/Au metallizationIBM·Filed 2003·Granted Nov 13, 2007·18 cites·20 claims
- 1973US8237288B1Enhanced electromigration resistance in TSV structure and designFAROOQ MUKTA G·Filed 2011·Granted Aug 7, 2012·3 cites·7 claims
- 2072US8386977B2Circuit design checking for three dimensional chip technologyIBM·Filed 2011·Granted Feb 26, 2013·3 cites·13 claims
- 2170US5953115AMethod and apparatus for imaging surface topography of a waferIBM·Filed 1997·Granted Sep 14, 1999·35 cites·18 claims
- 2270US2022362774A1Microfluidic chips with one or more viasIBM·Filed 2022·Application pending·0 cites
- 2369US8288270B2Enhanced electromigration resistance in TSV structure and designFAROOQ MUKTA G·Filed 2012·Granted Oct 16, 2012·2 cites·7 claims
- 2469US2024269209A1Hemp compositions and methods of making the sameLANDERS WILLIAM·Filed 2024·Application pending·0 cites
- 2568US9490197B2Three dimensional organic or glass interposerIBM·Filed 2014·Granted Nov 8, 2016·2 cites·19 claims
- 2666US6815346B2Unique feature design enabling structural integrity for advanced low k semiconductor chipsIBM·Filed 2003·Granted Nov 9, 2004·13 cites·7 claims
- 2759US2022125868A1Hemp compositions and methods of making the sameLANDERS WILLIAM·Filed 2021·Application pending·0 cites
- 2852US2015097274A1Through-silicon via structure and method for improving beol dielectric performanceIBM·Filed 2014·Application pending·0 cites
- 2951US6102776AApparatus and method for controlling polishing of integrated circuit substratesIBM·Filed 1999·Granted Aug 15, 2000·15 cites·17 claims
- 3049US2008073790A1METHOD OF FABRICATING A WIRE BOND PAD WITH Ni/Au METALLIZATIONIBM·Filed 2007·Application pending·0 cites
- 3149US2015069608A1Through-silicon via structure and method for improving beol dielectric performanceIBM·Filed 2013·Application pending·0 cites
- 3247US7678673B2Strengthening of a structure by infiltrationIBM·Filed 2007·Granted Mar 16, 2010·0 cites·20 claims
- 3346US6296717B1Regeneration of chemical mechanical polishing pads in-situIBM·Filed 1999·Granted Oct 2, 2001·12 cites·14 claims
- 3444US2008160752A1Method for chip to package interconnectIBM·Filed 2007·Application pending·0 cites
- 3541US8367543B2Structure and method to improve current-carrying capabilities of C4 jointsIBM·Filed 2006·Granted Feb 5, 2013·0 cites·9 claims
- 3640US2007080455A1Semiconductors and methods of makingIBM·Filed 2005·Application pending·0 cites
- 3736US6048745AMethod for mapping scratches in an oxide filmIBM·Filed 1997·Granted Apr 11, 2000·4 cites·14 claims
- 3836US5968841ADevice and method for preventing settlement of particles on a chemical-mechanical polishing padIBM·Filed 1997·Granted Oct 19, 1999·5 cites·52 claims
- 3935US6413870B1Process of removing CMP scratches by BPSG reflow and integrated circuit chip formed therebyIBM·Filed 1996·Granted Jul 2, 2002·4 cites·20 claims
- 4035US5897425AVertical polishing tool and methodIBM·Filed 1997·Granted Apr 27, 1999·8 cites·67 claims
- 4133US6291833B2Apparatus for mapping scratches in an oxide filmIBM·Filed 1999·Granted Sep 18, 2001·2 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →