Inventor · disambiguated record
Tin Tin Wee
Also filed as: WEE TIN TIN
16 granted patents·6 pending applications·74 citations·filing 1999–2019
91Inventor score
Files withQUALCOMM INC15CHARTERED SEMICONDUCTOR MFG2LOKE ALVIN LENG SUN2ADVANCE MICRO DEVICES INC1AVAGO TECHNOLOGIES GENERAL IP1
Top patents by PatentIndex Score
22 records- 0191US9977078B2Systems and methods for wafer-level loopback testQUALCOMM INC·Filed 2014·Granted May 22, 2018·8 cites·15 claims
- 0286US9614703B2Circuits and methods providing high-speed data link with equalizerQUALCOMM INC·Filed 2015·Granted Apr 4, 2017·6 cites·28 claims
- 0384US10114074B2Systems and methods for wafer-level loopback testQUALCOMM INC·Filed 2018·Granted Oct 30, 2018·2 cites·20 claims
- 0484US9767889B1Programmable pad capacitance for supporting bidirectional signaling from unterminated endpointsQUALCOMM INC·Filed 2017·Granted Sep 19, 2017·7 cites·20 claims
- 0584US9245870B1Systems and methods for providing data channels at a die-to-die interfaceQUALCOMM INC·Filed 2014·Granted Jan 26, 2016·7 cites·30 claims
- 0682US10410965B2Layout technique for middle-end-of-lineQUALCOMM INC·Filed 2018·Granted Sep 10, 2019·5 cites·7 claims
- 0775US9350339B2Systems and methods for clock distribution in a die-to-die interfaceQUALCOMM INC·Filed 2014·Granted May 24, 2016·3 cites·12 claims
- 0874US9244875B1Systems and methods for transition-minimized data bus inversionQUALCOMM INC·Filed 2014·Granted Jan 26, 2016·3 cites·20 claims
- 0969US8466536B2Shield-modulated tunable inductor deviceLOKE ALVIN LENG SUN·Filed 2010·Granted Jun 18, 2013·4 cites·26 claims
- 1064US6177304B1Self-aligned contact process using a poly-cap maskCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jan 23, 2001·25 cites·20 claims
- 1151US9654090B2Systems and methods for clock distribution in a die-to-die interfaceQUALCOMM INC·Filed 2016·Granted May 16, 2017·0 cites·17 claims
- 1249US9984011B2Termination schemes for multi-rank memory bus architecturesQUALCOMM INC·Filed 2016·Granted May 29, 2018·0 cites·21 claims
- 1349US7280002B2Method and apparatus for biasing a metal-oxide-semiconductor capacitor for capacitive tuningAVAGO TECHNOLOGIES GENERAL IP·Filed 2005·Granted Oct 9, 2007·2 cites·17 claims
- 1449US2019385948A1Layout technique for middle-end-of-lineQUALCOMM INC·Filed 2019·Application pending·0 cites
- 1548US10325845B2Layout technique for middle-end-of-lineQUALCOMM INC·Filed 2017·Granted Jun 18, 2019·0 cites·13 claims
- 1648US2017134191A1Circuits and Methods Providing High-Speed Data Link with EqualizerQUALCOMM INC·Filed 2017·Application pending·0 cites
- 1744US10044342B2Delay line for one shot pre-emphasisQUALCOMM INC·Filed 2016·Granted Aug 7, 2018·0 cites·26 claims
- 1839US2019304905A1Co-placement of resistor and other devices to improve area & performanceQUALCOMM INC·Filed 2018·Application pending·0 cites
- 1937US2010171547A1Pseudo bandgap voltage reference circuitFANG EMERSON S·Filed 2009·Application pending·0 cites
- 2036US2014159200A1High-density stacked planar metal-insulator-metal capacitor structure and method for manufacturing sameLOKE ALVIN LENG SUN·Filed 2012·Application pending·0 cites
- 2136US2011133719A1Voltage reference circuit operable with a low voltage supply and method for implementing sameADVANCE MICRO DEVICES INC·Filed 2009·Application pending·0 cites
- 2229US6093602AMethod to form polycide local interconnects between narrowly-spaced features while eliminating stringersCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 25, 2000·2 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →