Inventor · disambiguated record
Dharmesh Jawarani
Also filed as: JAWARANI DHARMESH
18 granted patents·7 pending applications·412 citations·filing 2003–2011
94Inventor score
Files withFREESCALE SEMICONDUCTOR INC14MATHEW LEO5WOODSIDE GROUP PTE LTD2ASTROWATT INC1JAWARANI DHARMESH1
Top patents by PatentIndex Score
25 records- 0196US7749884B2Method of forming an electronic device using a separation-enhancing speciesASTROWATT INC·Filed 2009·Granted Jul 6, 2010·265 cites·20 claims
- 0293US7521314B2Method for selective removal of a layerFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 21, 2009·29 cites·19 claims
- 0387US8043888B2Phase change memory cell with heater and method thereforFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Oct 25, 2011·16 cites·4 claims
- 0487US7235473B2Dual silicide semiconductor fabrication processFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 26, 2007·15 cites·14 claims
- 0584US7544576B2Diffusion barrier for nickel silicides in a semiconductor fabrication processFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Jun 9, 2009·11 cites·8 claims
- 0682US7544575B2Dual metal silicide scheme using a dual spacer processFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jun 9, 2009·12 cites·20 claims
- 0779US8076215B2Method of forming an electronic device using a separation techniqueMATHEW LEO·Filed 2009·Granted Dec 13, 2011·4 cites·16 claims
- 0876US7713801B2Method of making a semiconductor structure utilizing spacer removal and semiconductor structureTRIVEDI VISHAL P·Filed 2007·Granted May 11, 2010·5 cites·9 claims
- 0974US7105429B2Method of inhibiting metal silicide encroachment in a transistorFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Sep 12, 2006·17 cites·28 claims
- 1069US7927934B2SOI semiconductor device with body contact and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 19, 2011·4 cites·19 claims
- 1169US7510922B2Spacer T-gate structure for CoSi2 extendibilityFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 31, 2009·4 cites·20 claims
- 1269US7262105B2Semiconductor device with silicided source/drainsFREESCALE SEMICONDUCTOR INC·Filed 2003·Granted Aug 28, 2007·13 cites·25 claims
- 1368US7998822B2Semiconductor fabrication process including silicide stringer removal processingFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 16, 2011·2 cites·21 claims
- 1463US7235471B2Method for forming a semiconductor device having a silicide layerFREESCALE SEMICONDUCTOR INC·Filed 2004·Granted Jun 26, 2007·8 cites·19 claims
- 1562US8575588B2Phase change memory cell with heater and method thereforMATHEW LEO·Filed 2011·Granted Nov 5, 2013·2 cites·15 claims
- 1662US2012045866A1Method of forming an electronic device using a separation techniqueMATHEW LEO·Filed 2011·Application pending·0 cites
- 1761US7622339B2EPI T-gate structure for CoSi2 extendibilityFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Nov 24, 2009·2 cites·20 claims
- 1858US8247850B2Dual interlayer dielectric stressor integration with a sacrificial underlayer film stackJAWARANI DHARMESH·Filed 2007·Granted Aug 21, 2012·3 cites·20 claims
- 1950US7446006B2Semiconductor fabrication process including silicide stringer removal processingFREESCALE SEMICONDUCTOR INC·Filed 2005·Granted Nov 4, 2008·0 cites·7 claims
- 2050US2009159111A1Photovoltaic device having a textured metal silicide layerWOODSIDE GROUP PTE LTD·Filed 2007·Application pending·0 cites
- 2150US2009162966A1Structure and method of formation of a solar cellWOODSIDE GROUP PTE LTD·Filed 2007·Application pending·0 cites
- 2248US2009280588A1Method of forming an electronic device including removing a differential etch layerMATHEW LEO·Filed 2009·Application pending·0 cites
- 2345US2010227475A1Method of forming an electronic device using a separation techniqueMATHEW LEO·Filed 2010·Application pending·0 cites
- 2436US2007197011A1Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 2534US2005090067A1Silicide formation for a semiconductor deviceFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →