Inventor · disambiguated record
Boris A. Babaian
Also filed as: BABAIAN BORIS A
19 granted patents·1 pending application·522 citations·filing 1991–2011
95Inventor score
Files withELBRUS INTERNAT7ELBRUS INTERNAT LTD7ELBRUS INTERNATIONAL LTD2BABAIAN BORIS A1ELBRUS INTERNATIONAL1
Top patents by PatentIndex Score
20 records- 0190US6732220B2Method for emulating hardware features of a foreign architecture in a host operating system environmentELBRUS INTERNAT·Filed 2001·Granted May 4, 2004·91 cites·22 claims
- 0284US6820255B2Method for fast execution of translated binary code utilizing database cache for low-level code correspondenceELBRUS INTERNAT·Filed 2001·Granted Nov 16, 2004·65 cites·8 claims
- 0383US7143401B2Single-chip multiprocessor with cycle-precise program scheduling of parallel executionELBRUS INTERNAT·Filed 2001·Granted Nov 28, 2006·40 cites·6 claims
- 0478US6549903B1Integrity of tagged dataELBRUS INTERNAT LTD·Filed 2000·Granted Apr 15, 2003·41 cites·30 claims
- 0577US5958048AArchitectural support for software pipelining of nested loopsELBRUS INTERNATIONAL LTD·Filed 1996·Granted Sep 28, 1999·105 cites·24 claims
- 0674US8261250B2Single-chip multiprocessor with clock cycle-precise program scheduling of parallel executionBABAIAN BORIS A·Filed 2011·Granted Sep 4, 2012·5 cites·4 claims
- 0769US7065750B2Method and apparatus for preserving precise exceptions in binary translated codeELBRUS INTERNAT·Filed 2001·Granted Jun 20, 2006·24 cites·18 claims
- 0868US6564372B1Critical path optimization-unzippingELBRUS INTERNAT LTD·Filed 2000·Granted May 13, 2003·15 cites·7 claims
- 0965US7895587B2Single-chip multiprocessor with clock cycle-precise program scheduling of parallel executionELBRUS INTERNAT·Filed 2006·Granted Feb 22, 2011·3 cites·17 claims
- 1065US6516463B2Method for removing dependent store-load pair from critical pathELBRUS INTERNAT LTD·Filed 2001·Granted Feb 4, 2003·11 cites·4 claims
- 1162US6584611B2Critical path optimization—unload hard extended scalar blockELBRUS INTERNAT LTD·Filed 2001·Granted Jun 24, 2003·10 cites·19 claims
- 1261US5794029AArchitectural support for execution control of prologue and eplogue periods of loops in a VLIW processorELBRUS INTERNATIONAL LTD·Filed 1996·Granted Aug 11, 1998·45 cites·19 claims
- 1359US6526573B1Critical path optimization-optimizing branch operation insertionELBRUS INTERNAT LTD·Filed 2000·Granted Feb 25, 2003·8 cites·6 claims
- 1455US5889985AArray prefetch apparatus and methodELBRUS INTERNATIONAL·Filed 1996·Granted Mar 30, 1999·37 cites·20 claims
- 1550US7003650B2Method for prioritizing operations within a pipelined microprocessor based upon required resultsELBRUS INTERNAT·Filed 2001·Granted Feb 21, 2006·5 cites·7 claims
- 1648US7069412B2Method of using a plurality of virtual memory spaces for providing efficient binary compatibility between a plurality of source architectures and a single target architectureELBRUS INTERNAT·Filed 2003·Granted Jun 27, 2006·3 cites·3 claims
- 1737US2002046305A1Method for effective binary translation between different instruction sets using emulated supervisor flag and multiple page tablesFiled 2001·Application pending·0 cites
- 1825US6243822B1Method and system for asynchronous array loadingELBRUS INTERNAT LTD·Filed 1998·Granted Jun 5, 2001·1 cites·6 claims
- 1924US6560775B1Branch preparationELBRUS INTERNAT LTD·Filed 1998·Granted May 6, 2003·3 cites·15 claims
- 2024US5418975AWide instruction word architecture central processorINST TOCHNOI MEK I VYCHISLITEL·Filed 1991·Granted May 23, 1995·10 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →