Inventor · disambiguated record
Joyce C. Liu
Also filed as: LIU JOYCE · LIU JOYCE C
24 granted patents·7 pending applications·440 citations·filing 1999–2024
96Inventor score
Top patents by PatentIndex Score
31 records- 0193US6348076B1Slurry for mechanical polishing (CMP) of metals and use thereofIBM·Filed 1999·Granted Feb 19, 2002·147 cites·26 claims
- 0289US6720249B1Protective hardmask for producing interconnect structuresIBM·Filed 2000·Granted Apr 13, 2004·59 cites·29 claims
- 0386US6821890B2Method for improving adhesion to copperIBM·Filed 2001·Granted Nov 23, 2004·37 cites·16 claims
- 0483US6838347B1Method for reducing line edge roughness of oxide material using chemical oxide removalIBM·Filed 2003·Granted Jan 4, 2005·28 cites·12 claims
- 0571US6828187B1Method for uniform reactive ion etching of dual pre-doped polysilicon regionsIBM·Filed 2004·Granted Dec 7, 2004·17 cites·20 claims
- 0671US6518151B1Dual layer hard mask for eDRAM gate etch processIBM·Filed 2001·Granted Feb 11, 2003·14 cites·17 claims
- 0770US6703312B2Method of forming active devices of different gatelengths using lithographic printed gate images of same lengthIBM·Filed 2002·Granted Mar 9, 2004·16 cites·20 claims
- 0869US8907494B2Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structuresIBM·Filed 2013·Granted Dec 9, 2014·2 cites·15 claims
- 0969US6271595B1Method for improving adhesion to copperIBM·Filed 1999·Granted Aug 7, 2001·30 cites·15 claims
- 1068US6429067B1Dual mask process for semiconductor devicesIBM·Filed 2001·Granted Aug 6, 2002·15 cites·10 claims
- 1166US6221780B1Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 1999·Granted Apr 24, 2001·27 cites·26 claims
- 1264US9252133B2Electrical leakage reduction in stacked integrated circuits having through-silicon-via (TSV) structuresGLOBALFOUNDRIES INC·Filed 2014·Granted Feb 2, 2016·1 cites·5 claims
- 1363US7858485B2Structure and method for manufacturing trench capacitanceIBM·Filed 2008·Granted Dec 28, 2010·2 cites·9 claims
- 1460US7081393B2Reduced dielectric constant spacer materials integration for high speed logic gatesIBM·Filed 2004·Granted Jul 25, 2006·8 cites·20 claims
- 1560US6727589B2Dual damascene flowable oxide insulation structure and metallic barrierIBM·Filed 2000·Granted Apr 27, 2004·6 cites·24 claims
- 1660US2025325221A1Cervix stiffness measurement system and methodPOGUE EMILY·Filed 2024·Application pending·0 cites
- 1759US2024342834A1Apparatus of Inner Light Layer Formed by Multibeam Interference for Processing Object in Optical Turbid MediumLIU JOYCE·Filed 2024·Application pending·0 cites
- 1856US2022258277A1Laser Beam Processing Apparatuses and Correspondent Method Using Multi-beam InterferenceLIU JOYCE·Filed 2021·Application pending·0 cites
- 1954US10446484B2Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variabilityGLOBALFOUNDRIES INC·Filed 2017·Granted Oct 15, 2019·0 cites·15 claims
- 2052US9847290B1Through-silicon via with improved substrate contact for reduced through-silicon via (TSV) capacitance variabilityGLOBALFOUNDRIES INC·Filed 2016·Granted Dec 19, 2017·0 cites·13 claims
- 2152US6479884B2Interim oxidation of silsesquioxane dielectric for dual damascene processIBM·Filed 2001·Granted Nov 12, 2002·4 cites·4 claims
- 2251US12103068B2Smart trim die assemblyMAGNA INT INC·Filed 2020·Granted Oct 1, 2024·0 cites·18 claims
- 2348US6348736B1In situ formation of protective layer on silsesquioxane dielectric for dual damascene processIBM·Filed 1999·Granted Feb 19, 2002·13 cites·14 claims
- 2446US9728506B2Strain engineering devices using partial depth films in through-substrate viasGLOBALFOUNDRIES INC·Filed 2015·Granted Aug 8, 2017·0 cites·18 claims
- 2546US2009104776A1Methods for forming nested and isolated lines in semiconductor devicesIBM·Filed 2007·Application pending·0 cites
- 2645US6329280B1Interim oxidation of silsesquioxane dielectric for dual damascene processIBM·Filed 1999·Granted Dec 11, 2001·10 cites·18 claims
- 2744US2008194112A1Method and system for plasma etching having improved across-wafer etch uniformityIBM·Filed 2007·Application pending·0 cites
- 2842US10095115B2Forming edge etch protection using dual layer of positive-negative tone resistsGLOBALFOUNDRIES INC·Filed 2016·Granted Oct 9, 2018·0 cites·15 claims
- 2940US2008182372A1Method of forming disposable spacers for improved stressed nitride film effectivenessIBM·Filed 2007·Application pending·0 cites
- 3037US2018047807A1Deep trench capacitors with a diffusion padGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 3134US6284574B1Method of producing heat dissipating structure for semiconductor devicesIBM·Filed 1999·Granted Sep 4, 2001·4 cites·5 claims
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