Inventor · disambiguated record
Gary L. Whisenhunt
Also filed as: WHISENHUNT GARY · WHISENHUNT GARY L · WHISENHUNT GARY LEE
23 granted patents·2 pending applications·365 citations·filing 1998–2012
95Inventor score
Technology areasG06F
Top patents by PatentIndex Score
25 records- 0195US6792502B1Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operationFREESCALE SEMICONDUCTOR INC·Filed 2000·Granted Sep 14, 2004·172 cites·39 claims
- 0290US8261047B2Qualification of conditional debug instructions based on addressMOYER WILLIAM C·Filed 2008·Granted Sep 4, 2012·22 cites·20 claims
- 0389US8615644B2Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource conditionBRUCE BECKY·Filed 2010·Granted Dec 24, 2013·18 cites·13 claims
- 0484US9047079B2Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource conditionBRUCE BECKY·Filed 2012·Granted Jun 2, 2015·10 cites·7 claims
- 0582US7849247B2Interrupt controller for accelerated interrupt handling in a data processing system and method thereofFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Dec 7, 2010·11 cites·18 claims
- 0681US8117618B2Forward progress mechanism for a multithreaded processorHOLLOWAY DAVID C·Filed 2007·Granted Feb 14, 2012·16 cites·20 claims
- 0778US8095831B2Programmable error actions for a cache in a data processing systemMOYER WILLIAM C·Filed 2008·Granted Jan 10, 2012·8 cites·17 claims
- 0877US7827360B2Cache locking device and methods thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Nov 2, 2010·11 cites·20 claims
- 0972US7941499B2Interprocessor message transmission via coherency-based interconnectFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted May 10, 2011·6 cites·20 claims
- 1072US6145122ADevelopment interface for a data processorMOTOROLA INC·Filed 1998·Granted Nov 7, 2000·68 cites·65 claims
- 1171US8539485B2Polling using reservation mechanismSNYDER MICHAEL D·Filed 2007·Granted Sep 17, 2013·6 cites·17 claims
- 1271US7689815B2Debug instruction for use in a data processing systemFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Mar 30, 2010·5 cites·14 claims
- 1368US9442870B2Interrupt priority management using partition-based priority blocking processor registersMARIETTA BRYAN D·Filed 2012·Granted Sep 13, 2016·2 cites·20 claims
- 1467US9436626B2Processor interrupt interface with interrupt partitioning and virtualization enhancementsMARIETTA BRYAN D·Filed 2012·Granted Sep 6, 2016·2 cites·20 claims
- 1567US9229884B2Virtualized instruction extensions for system partitioningMARIETTA BRYAN D·Filed 2012·Granted Jan 5, 2016·2 cites·18 claims
- 1663US8627471B2Permissions checking for data processing instructionsMOYER WILLIAM C·Filed 2008·Granted Jan 7, 2014·2 cites·21 claims
- 1762US9213665B2Data processor for processing a decorated storage notifyMOYER WILLIAM C·Filed 2008·Granted Dec 15, 2015·2 cites·22 claims
- 1856US8832702B2Thread de-emphasis instruction for multithreaded processorBRUCE KLAS M·Filed 2007·Granted Sep 9, 2014·2 cites·20 claims
- 1951US9395983B2Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operationMOYER WILLIAM C·Filed 2008·Granted Jul 19, 2016·0 cites·24 claims
- 2048US2010049956A1Debug instruction for use in a multi-threaded data processing systemMOYER WILLIAM C·Filed 2008·Application pending·0 cites
- 2147US9152587B2Virtualized interrupt delay mechanismMARIETTA BRYAN D·Filed 2012·Granted Oct 6, 2015·0 cites·21 claims
- 2246US7805581B2Multiple address and arithmetic bit-mode data processing device and methods thereofFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Sep 28, 2010·0 cites·20 claims
- 2346US7702881B2Method and system for data transfers across different address spacesFREESCALE SEMICONDUCTOR INC·Filed 2007·Granted Apr 20, 2010·0 cites·20 claims
- 2446US2009019232A1Specification of coherence domain during address translationFREESCALE SEMICONDUCTOR INC·Filed 2007·Application pending·0 cites
- 2545US7584344B2Instruction for conditionally yielding to a ready thread based on priority criteriaFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Sep 1, 2009·0 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →