Inventor · disambiguated record
Siddharth K. Alur
Also filed as: ALUR SIDDHARTH · ALUR SIDDHARTH K
22 granted patents·6 pending applications·48 citations·filing 2015–2024
92Inventor score
Top patents by PatentIndex Score
28 records- 0197US10424530B1Electrical interconnections with improved compliance due to stress relaxation and method of makingINTEL CORP·Filed 2018·Granted Sep 24, 2019·28 cites·21 claims
- 0296US11664290B2Package with underfill containment barrierINTEL CORP·Filed 2021·Granted May 30, 2023·3 cites·20 claims
- 0390US10020262B2High resolution solder resist material for silicon bridge applicationINTEL CORP·Filed 2016·Granted Jul 10, 2018·7 cites·18 claims
- 0489US11158558B2Package with underfill containment barrierINTEL CORP·Filed 2016·Granted Oct 26, 2021·5 cites·16 claims
- 0584US12327773B2Package with underfill containment barrierINTEL CORP·Filed 2024·Granted Jun 10, 2025·0 cites·20 claims
- 0684US10685850B2High density organic interconnect structuresINTEL CORP·Filed 2016·Granted Jun 16, 2020·3 cites·11 claims
- 0784US2024355641A1High density organic interconnect structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 0880US12062551B2High density organic interconnect structuresINTEL CORP·Filed 2023·Granted Aug 13, 2024·0 cites·20 claims
- 0980US11935805B2Package with underfill containment barrierINTEL CORP·Filed 2023·Granted Mar 19, 2024·0 cites·20 claims
- 1075US11631595B2High density organic interconnect structuresINTEL CORP·Filed 2021·Granted Apr 18, 2023·0 cites·11 claims
- 1173US10741947B2Plated through hole socketing coupled to a solder ball to engage with a pinINTEL CORP·Filed 2018·Granted Aug 11, 2020·2 cites·23 claims
- 1271US11195727B2High density organic interconnect structuresINTEL CORP·Filed 2020·Granted Dec 7, 2021·0 cites·18 claims
- 1357US2025293122A1Multi-die assemblies with glass support structuresINTEL CORP·Filed 2024·Application pending·0 cites
- 1456US10903137B2Electrical interconnections with improved compliance due to stress relaxation and method of makingINTEL CORP·Filed 2019·Granted Jan 26, 2021·0 cites·20 claims
- 1551US10727184B2Microelectronic device including non-homogeneous build-up dielectricINTEL CORP·Filed 2018·Granted Jul 28, 2020·0 cites·12 claims
- 1651US9728500B2Integrated circuit surface layer with adhesion-functional groupINTEL CORP·Filed 2015·Granted Aug 8, 2017·0 cites·13 claims
- 1751US2024114622A1Embedded passives with cavity sidewall interconnect in glass core architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1849US11196165B2Low z-height, ultra-low dielectric constant air cavity based and multi-core/highly asymmetric antenna substrate architectures for electrical performance improvements in 5G mm-wave applicationsINTEL CORP·Filed 2018·Granted Dec 7, 2021·0 cites·25 claims
- 1949US10384431B2Methods for forming a substrate structure for an electrical component and an apparatus for applying pressure to an electrically insulating laminate located on a core substrateINTEL CORP·Filed 2017·Granted Aug 20, 2019·0 cites·24 claims
- 2049US2017301619A1Integrated circuit surface layer with adhesion-functional groupINTEL CORP·Filed 2017·Application pending·0 cites
- 2149US2024070366A1Adaptive trace width in multi-layer substrate packageINTEL CORP·Filed 2022·Application pending·0 cites
- 2248US12224253B2Magnetic inductor device and methodINTEL CORP·Filed 2021·Granted Feb 11, 2025·0 cites·27 claims
- 2346US11508636B2Multi-layer solution based deposition of dielectrics for advanced substrate architecturesINTEL CORP·Filed 2018·Granted Nov 22, 2022·0 cites·9 claims
- 2446US11075130B2Package substrate having polymer-derived ceramic coreINTEL CORP·Filed 2017·Granted Jul 27, 2021·0 cites·20 claims
- 2543US12334447B2Lithographically defined vertical interconnect access (VIA) for a bridge die first level interconnect (FLI)INTEL CORP·Filed 2019·Granted Jun 17, 2025·0 cites·23 claims
- 2642US11393762B2Formation of tall metal pillars using multiple photoresist layersINTEL CORP·Filed 2017·Granted Jul 19, 2022·0 cites·19 claims
- 2740US10553453B2Systems and methods for semiconductor packages using photoimageable layersINTEL CORP·Filed 2016·Granted Feb 4, 2020·0 cites·20 claims
- 2834US2017174894A1Stress tolerant composite material and architectureCHAVALI SRI CHAITRA·Filed 2015·Application pending·0 cites
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →