Inventor · disambiguated record
Suresh Srinivas
Also filed as: SRINIVAS SURESH
16 granted patents·8 pending applications·94 citations·filing 2003–2024
92Inventor score
Technology areasG06F
Top patents by PatentIndex Score
24 records- 0190US8762127B2Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environmentINTEL CORP·Filed 2013·Granted Jun 24, 2014·13 cites·19 claims
- 0287US9189233B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSASANKA RUCHIRA·Filed 2012·Granted Nov 17, 2015·13 cites·16 claims
- 0386US10725755B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsINTEL CORP·Filed 2017·Granted Jul 28, 2020·4 cites·17 claims
- 0485US9417855B2Instruction and logic to perform dynamic binary translationKANHERE ABHAY S·Filed 2011·Granted Aug 16, 2016·11 cites·19 claims
- 0583US8972994B2Method and apparatus to bypass object lock by speculative execution of generated bypass code shell based on bypass failure threshold in managed runtime environmentSRINIVAS SURESH·Filed 2009·Granted Mar 3, 2015·15 cites·17 claims
- 0681US10120663B2Inter-architecture compatability module to allow code module of one architecture to use library module of another architectureINTEL CORP·Filed 2014·Granted Nov 6, 2018·7 cites·20 claims
- 0779US9672019B2Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threadsSAGER DAVID J·Filed 2010·Granted Jun 6, 2017·6 cites·18 claims
- 0875US7415701B2Methods and apparatus to support mixed-mode execution within a single instruction set architecture process of a virtual machineINTEL CORP·Filed 2005·Granted Aug 19, 2008·11 cites·12 claims
- 0973US7991956B2Providing application-level information for use in cache managementINTEL CORP·Filed 2007·Granted Aug 2, 2011·6 cites·17 claims
- 1071US9542191B2Hardware profiling mechanism to enable page level automatic binary translationCAPRIOLI PAUL·Filed 2012·Granted Jan 10, 2017·3 cites·20 claims
- 1166US9529645B2Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target codeINTEL CORP·Filed 2015·Granted Dec 27, 2016·1 cites·17 claims
- 1261US9170789B2Analyzing potential benefits of vectorizationINTEL CORP·Filed 2013·Granted Oct 27, 2015·1 cites·17 claims
- 1359US7991965B2Technique for using memory attributesINTEL CORP·Filed 2006·Granted Aug 2, 2011·1 cites·35 claims
- 1458US8775153B2Transitioning from source instruction set architecture (ISA) code to translated code in a partial emulation environmentWINKEL SEBASTIAN·Filed 2009·Granted Jul 8, 2014·2 cites·24 claims
- 1557US2025307174A1Circuitry and methods for reducing instruction translation lookaside buffer overheads for dynamic code librariesINTEL CORP·Filed 2024·Application pending·0 cites
- 1654US8812792B2Technique for using memory attributesINTEL CORP·Filed 2013·Granted Aug 19, 2014·0 cites·11 claims
- 1749US2017212825A1Hardware profiling mechanism to enable page level automatic binary translationINTEL CORP·Filed 2017·Application pending·0 cites
- 1847US8560781B2Technique for using memory attributesJACOBSON QUINN A·Filed 2011·Granted Oct 15, 2013·0 cites·34 claims
- 1945US2008244544A1Using hardware checkpoints to support software based speculationNEELAKANTAM NAVEEN·Filed 2007·Application pending·0 cites
- 2042US2008052691A1Communicating with and recovering state information from a dynamic translatorNEELAKANTAM NAVEEN·Filed 2006·Application pending·0 cites
- 2141US2007162475A1Method and apparatus for hardware-based dynamic escape detection in managed run-time environmentsINTEL CORP·Filed 2005·Application pending·0 cites
- 2240US2005132336A1Analyzing software performance data using hierarchical models of software structureINTEL CORP·Filed 2003·Application pending·0 cites
- 2338US2013262779A1Profile-based hardware prefetchingBOBBA JAYARAM·Filed 2012·Application pending·0 cites
- 2436US2007156967A1Identifying delinquent object chains in a managed run time environmentBOND MICHAEL·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →