Assignee
VERISITY LTD
IL·12 granted patents·723 citations·filing 1998–2005
Top patents by PatentIndex Score
12 records- 0197US6182258B1Method and apparatus for test generation during circuit designVERISITY LTD·Filed 1998·Granted Jan 30, 2001·240 cites·35 claims
- 0296US6347388B1Method and apparatus for test generation during circuit designVERISITY LTD·Filed 2000·Granted Feb 12, 2002·94 cites·10 claims
- 0395US6530054B2Method and apparatus for test generation during circuit designVERISITY LTD·Filed 2002·Granted Mar 4, 2003·82 cites·8 claims
- 0490US7284177B2Method and apparatus for functionally verifying a physical device under testVERISITY LTD·Filed 2005·Granted Oct 16, 2007·28 cites·20 claims
- 0590US6684359B2System and method for test generation with dynamic constraints using static analysisVERISITY LTD·Filed 2001·Granted Jan 27, 2004·56 cites·12 claims
- 0684US6499132B1System and method for analyzing temporal expressionsVERISITY LTD·Filed 2001·Granted Dec 24, 2002·47 cites·12 claims
- 0781US6675138B1System and method for measuring temporal coverage detectionVERISITY LTD·Filed 1999·Granted Jan 6, 2004·60 cites·20 claims
- 0879US6920583B1System and method for compiling temporal expressionsVERISITY LTD·Filed 2001·Granted Jul 19, 2005·32 cites·17 claims
- 0977US6907599B1Synthesis of verification languagesVERISITY LTD·Filed 2001·Granted Jun 14, 2005·29 cites·22 claims
- 1076US6519727B2System and method for applying flexible constraintsVERISITY LTD·Filed 2001·Granted Feb 11, 2003·18 cites·15 claims
- 1169US6219809B1System and method for applying flexible constraintsVERISITY LTD·Filed 1999·Granted Apr 17, 2001·28 cites·12 claims
- 1255US6918076B2Method for providing bitwise constraints for test generationVERISITY LTD·Filed 2001·Granted Jul 12, 2005·9 cites·13 claims
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →