Assignee
UNITED TEST & ASSEMBLY CT LTD
SG·15 granted patents·9 pending applications·135 citations·filing 2002–2009
Top patents by PatentIndex Score
24 records- 0191US7323769B2High performance chip scale leadframe package with thermal dissipating structure and annular element and method of manufacturing packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted Jan 29, 2008·28 cites·20 claims
- 0286US7375416B2Leadframe enhancement and method of producing a multi-row semiconductor packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted May 20, 2008·15 cites·9 claims
- 0386US7339278B2Cavity chip packageUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted Mar 4, 2008·21 cites·23 claims
- 0480US7824960B2Method of assembling a silicon stack semiconductor packageUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Granted Nov 2, 2010·17 cites·19 claims
- 0569US7723833B2Stacked die packagesUNITED TEST & ASSEMBLY CT LTD·Filed 2007·Granted May 25, 2010·5 cites·18 claims
- 0669US7023076B2Multiple chip semiconductor packagesUNITED TEST & ASSEMBLY CT LTD·Filed 2003·Granted Apr 4, 2006·20 cites·26 claims
- 0767US7345357B2High density chip scale leadframe package and method of manufacturing the packageUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Mar 18, 2008·3 cites·7 claims
- 0865US7830006B2Structurally-enhanced integrated circuit package and method of manufactureUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Nov 9, 2010·4 cites·10 claims
- 0962US7476569B2Leadframe enhancement and method of producing a multi-row semiconductor packageUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Granted Jan 13, 2009·2 cites·7 claims
- 1058US7816775B2Multi-die IC package and manufacturing methodUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Granted Oct 19, 2010·2 cites·14 claims
- 1153US7642638B2Inverted lead frame in substrateUNITED TEST & ASSEMBLY CT LTD·Filed 2007·Granted Jan 5, 2010·4 cites·26 claims
- 1248US7129115B2Packaging of a microchip deviceUNITED TEST & ASSEMBLY CT LTD·Filed 2002·Granted Oct 31, 2006·4 cites·13 claims
- 1347US6921974B2Packaged device with thermal enhancement and method of packagingUNITED TEST & ASSEMBLY CT LTD·Filed 2003·Granted Jul 26, 2005·6 cites·23 claims
- 1446US7443041B2Packaging of a microchip deviceUNITED TEST & ASSEMBLY CT LTD·Filed 2002·Granted Oct 28, 2008·4 cites·4 claims
- 1546US2010109169A1Semiconductor package and method of making the sameUNITED TEST & ASSEMBLY CT LTD·Filed 2009·Application pending·0 cites
- 1645US7504715B2Packaging of a microchip deviceUNITED TEST & ASSEMBLY CT LTD·Filed 2006·Granted Mar 17, 2009·0 cites·6 claims
- 1744US2010102436A1Shrink package on boardUNITED TEST & ASSEMBLY CT LTD·Filed 2009·Application pending·0 cites
- 1843US2009236726A1Package-on-package semiconductor structureUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Application pending·0 cites
- 1937US2009165815A1Avoiding electrical shorts in packagingUNITED TEST & ASSEMBLY CT LTD·Filed 2008·Application pending·0 cites
- 2036US2004140557A1Wl-bga for MEMS/MOEMS devicesUNITED TEST & ASSEMBLY CT LTD·Filed 2003·Application pending·0 cites
- 2136US2004140475A13D MEMS/MOEMS packageUNITED TEST & ASSEMBLY CT LTD·Filed 2003·Application pending·0 cites
- 2233US2007132081A1Multiple stacked die window csp package and method of manufactureUNITED TEST & ASSEMBLY CT LTD·Filed 2005·Application pending·0 cites
- 2332US2004195697A1Method of packaging circuit device and packaged deviceUNITED TEST & ASSEMBLY CT LTD·Filed 2003·Application pending·0 cites
- 2432US2009008796A1Copper on organic solderability preservative (osp) interconnectUNITED TEST & ASSEMBLY CT LTD·Filed 2007·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →