Assignee
TRAN JONATHAN SON HUNG
US·3 granted patents·9 citations·filing 2011–2011
Top patents by PatentIndex Score
3 records- 0188US8904260B2Robust hamming code implementation for soft error detection, correction, and reporting in a multi-level cache system using dual banking memory schemeTRAN JONATHAN SON HUNG·Filed 2011·Granted Dec 2, 2014·7 cites·7 claims
- 0280US8707127B2Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routinesTRAN JONATHAN SON HUNG·Filed 2011·Granted Apr 22, 2014·2 cites·4 claims
- 0354US9075744B2Performance and power improvement on DMA writes to level two combined cache/SRAM that is caused in level one data cache and line is valid and dirtyTRAN JONATHAN SON HUNG·Filed 2011·Granted Jul 7, 2015·0 cites·4 claims
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