Assignee
Sinha Arani
US·0 granted patents·2 pending applications·0 citations·filing 2015–2017
Top patents by PatentIndex Score
2 records- 0132US2018024192A1Test pattern count reduction for testing delay faultsSinha Arani·Filed 2017·Application pending·0 cites
- 0228US2016275224A1Apparatus and method for generating a reduced number of test vectors and inserting test points for a logic circuitSinha Arani·Filed 2015·Application pending·0 cites
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