Assignee
SIFIVE INC
US·93 granted patents·60 pending applications·74 citations·filing 2018–2025
Top patents by PatentIndex Score
153 records- 0195US10922462B1Intellectual property block validation and design integration for integrated circuitsSIFIVE INC·Filed 2019·Granted Feb 16, 2021·42 cites·18 claims
- 0290US11630930B2Generation of dynamic design flows for integrated circuitsSIFIVE INC·Filed 2021·Granted Apr 18, 2023·2 cites·20 claims
- 0389US11023375B1Data cache with hybrid writeback and writethroughSIFIVE INC·Filed 2020·Granted Jun 1, 2021·3 cites·20 claims
- 0487US11321511B2Reset crossing and clock crossing interface for integrated circuit generationSIFIVE INC·Filed 2021·Granted May 3, 2022·2 cites·20 claims
- 0586US11048837B2Generation of dynamic design flows for integrated circuitsSIFIVE INC·Filed 2019·Granted Jun 29, 2021·4 cites·27 claims
- 0685US11675945B2Reset crossing and clock crossing interface for integrated circuit generationSIFIVE INC·Filed 2022·Granted Jun 13, 2023·1 cites·20 claims
- 0783US11296683B2Low-swing Schmitt triggersSIFIVE INC·Filed 2020·Granted Apr 5, 2022·2 cites·9 claims
- 0883US11055457B1Pad ring generation for integrated circuitsSIFIVE INC·Filed 2020·Granted Jul 6, 2021·2 cites·20 claims
- 0983US2026072689A1Macro-op fusion for pipelined architecturesSIFIVE INC·Filed 2025·Application pending·0 cites
- 1082US2026064426A1Technologies for prediction-based register renamingSIFIVE INC·Filed 2025·Application pending·0 cites
- 1180US11861365B2Macro-op fusionSIFIVE INC·Filed 2021·Granted Jan 2, 2024·1 cites·20 claims
- 1280US11025237B1Zero static high-speed, low power level shifterSIFIVE INC·Filed 2020·Granted Jun 1, 2021·2 cites·16 claims
- 1380US10965278B1Cross-coupled high-speed, low power level shifterSIFIVE INC·Filed 2020·Granted Mar 30, 2021·2 cites·19 claims
- 1480US10902171B1Clock crossing interface for integrated circuit generationSIFIVE INC·Filed 2019·Granted Jan 26, 2021·3 cites·20 claims
- 1580US2026017199A1Data storage in non-inclusive cacheSIFIVE INC·Filed 2025·Application pending·0 cites
- 1680US2025383877A1Fusion with destructive instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 1777US2026010372A1Technologies for interconnect address remapper with event recognition and register managementSIFIVE INC·Filed 2025·Application pending·0 cites
- 1876US12066941B2Method for executing atomic memory operations when contestedSIFIVE INC·Filed 2022·Granted Aug 20, 2024·0 cites·20 claims
- 1976US11467962B2Method for executing atomic memory operations when contestedSIFIVE INC·Filed 2020·Granted Oct 11, 2022·1 cites·15 claims
- 2076US2025335367A1Logging guest physical address for memory access faultsSIFIVE INC·Filed 2025·Application pending·0 cites
- 2175US12566606B2Prefetching cache blocks based on an address for a group and a bit fieldSIFIVE INC·Filed 2023·Granted Mar 3, 2026·0 cites·14 claims
- 2275US12197335B2Canceling prefetch of cache blocks based on an address and a bit fieldSIFIVE INC·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 2374US12487829B2Macro-op fusion for pipelined architecturesSIFIVE INC·Filed 2024·Granted Dec 2, 2025·0 cites·20 claims
- 2474US12430252B2Data storage in non-inclusive cacheSIFIVE INC·Filed 2023·Granted Sep 30, 2025·0 cites·18 claims
- 2574US12248401B2Eviction operations based on eviction message types of different prioritiesSIFIVE INC·Filed 2023·Granted Mar 11, 2025·0 cites·22 claims
- 2674US11914933B2Generation of dynamic design flows for integrated circuitsSIFIVE INC·Filed 2023·Granted Feb 27, 2024·0 cites·20 claims
- 2774US2025110896A1Downgrading a permission associated with data stored in a cacheSIFIVE INC·Filed 2024·Application pending·0 cites
- 2873US12293192B2Bundling and dynamic allocation of register blocks for vector instructionsSIFIVE INC·Filed 2023·Granted May 6, 2025·0 cites·21 claims
- 2973US11922101B2Integrated circuits as a serviceSIFIVE INC·Filed 2023·Granted Mar 5, 2024·0 cites·20 claims
- 3073US2026056736A1Matrix multiply engineSIFIVE INC·Filed 2024·Application pending·0 cites
- 3172US12554504B2Dependency tracking and chaining for vector instructionsSIFIVE INC·Filed 2023·Granted Feb 17, 2026·0 cites·17 claims
- 3272US12259825B2Concurrent support for multiple cache inclusivity schemes using low priority evict operationsSIFIVE INC·Filed 2023·Granted Mar 25, 2025·0 cites·20 claims
- 3372US12204462B2Downgrading a permission associated with data stored in a cacheSIFIVE INC·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 3472US11687455B2Data cache with hybrid writeback and writethroughSIFIVE INC·Filed 2022·Granted Jun 27, 2023·0 cites·20 claims
- 3571US12417103B2Fusion with destructive instructionsSIFIVE INC·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 3671US2025147761A1Canceling prefetch of cache blocks based on an address and a bit fieldSIFIVE INC·Filed 2025·Application pending·0 cites
- 3770US12561246B2Virtualized cachesSIFIVE INC·Filed 2022·Granted Feb 24, 2026·0 cites·20 claims
- 3870US12306772B2Orderability of operationsSIFIVE INC·Filed 2023·Granted May 20, 2025·0 cites·20 claims
- 3970US12260217B2Using renamed registers to support multiple vset{i}vl{i} instructionsSIFIVE INC·Filed 2023·Granted Mar 25, 2025·0 cites·16 claims
- 4070US11847060B2Data cache with prediction hints for cache hitsSIFIVE INC·Filed 2023·Granted Dec 19, 2023·0 cites·20 claims
- 4170US10996952B2Macro-op fusionSIFIVE INC·Filed 2018·Granted May 4, 2021·1 cites·39 claims
- 4270US2025278271A1Transfer buffer between a scalar pipeline and vector pipelineSIFIVE INC·Filed 2025·Application pending·0 cites
- 4369US12386764B2Selective transfer of data including a priority byteSIFIVE INC·Filed 2023·Granted Aug 12, 2025·0 cites·20 claims
- 4469US12373210B2Transfer buffer between a scalar pipeline and vector pipelineSIFIVE INC·Filed 2023·Granted Jul 29, 2025·0 cites·20 claims
- 4569US2025181355A1Dependency tracking and chaining for vector instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 4669US2025181507A1Eviction operations based on eviction message types of different prioritiesSIFIVE INC·Filed 2025·Application pending·0 cites
- 4769US2025251939A1Bundling and dynamic allocation of register blocks for vector instructionsSIFIVE INC·Filed 2025·Application pending·0 cites
- 4868US12204458B1Translation lookaside buffer probing preventionSIFIVE INC·Filed 2023·Granted Jan 21, 2025·0 cites·20 claims
- 4968US2026056737A1Matrix multiply engineSIFIVE INC·Filed 2025·Application pending·0 cites
- 5068US2025173281A1Orderability of operationsSIFIVE INC·Filed 2025·Application pending·0 cites
Showing the top 50 of 153 patent records by PatentIndex Score.
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