Assignee
RJ MEARS LLC
US·25 granted patents·23 pending applications·2,955 citations·filing 2000–2006
Top patents by PatentIndex Score
48 records- 0199US7265002B2Method for making a semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelRJ MEARS LLC·Filed 2005·Granted Sep 4, 2007·114 cites·39 claims
- 0298US7288457B2Method for making semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regionsRJ MEARS LLC·Filed 2004·Granted Oct 30, 2007·111 cites·46 claims
- 0398US7279701B2Semiconductor device comprising a superlattice with upper portions extending above adjacent upper portions of source and drain regionsRJ MEARS LLC·Filed 2004·Granted Oct 9, 2007·119 cites·46 claims
- 0498US7279699B2Integrated circuit comprising a waveguide having an energy band engineered superlatticeRJ MEARS LLC·Filed 2004·Granted Oct 9, 2007·110 cites·30 claims
- 0598US7229902B2Method for making a semiconductor device including a superlattice with regions defining a semiconductor junctionRJ MEARS LLC·Filed 2005·Granted Jun 12, 2007·110 cites·26 claims
- 0698US7227174B2Semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junctionRJ MEARS LLC·Filed 2005·Granted Jun 5, 2007·113 cites·20 claims
- 0798US7202494B2FINFET including a superlatticeRJ MEARS LLC·Filed 2006·Granted Apr 10, 2007·140 cites·23 claims
- 0898US7153763B2Method for making a semiconductor device including band-engineered superlattice using intermediate annealingRJ MEARS LLC·Filed 2005·Granted Dec 26, 2006·119 cites·31 claims
- 0998US7109052B2Method for making an integrated circuit comprising a waveguide having an energy band engineered superlatticeRJ MEARS LLC·Filed 2004·Granted Sep 19, 2006·113 cites·30 claims
- 1098US7071119B2Method for making a semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Jul 4, 2006·112 cites·26 claims
- 1198US7045813B2Semiconductor device including a superlattice with regions defining a semiconductor junctionRJ MEARS LLC·Filed 2005·Granted May 16, 2006·110 cites·20 claims
- 1298US7045377B2Method for making a semiconductor device including a superlattice and adjacent semiconductor layer with doped regions defining a semiconductor junctionRJ MEARS LLC·Filed 2005·Granted May 16, 2006·110 cites·20 claims
- 1398US7034329B2Semiconductor device including band-engineered superlattice having 3/1-5/1 germanium layer structureRJ MEARS LLC·Filed 2004·Granted Apr 25, 2006·114 cites·26 claims
- 1498US7018900B2Method for making a semiconductor device comprising a superlattice channel vertically stepped above source and drain regionsRJ MEARS LLC·Filed 2004·Granted Mar 28, 2006·114 cites·48 claims
- 1598US6993222B2Optical filter device with aperiodically arranged grating elementsRJ MEARS LLC·Filed 2003·Granted Jan 31, 2006·113 cites·22 claims
- 1698US6958486B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 25, 2005·114 cites·71 claims
- 1798US6952018B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Oct 4, 2005·112 cites·26 claims
- 1898US6927413B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Aug 9, 2005·113 cites·26 claims
- 1998US6897472B2Semiconductor device including MOSFET having band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted May 24, 2005·153 cites·71 claims
- 2098US6891188B2Semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted May 10, 2005·123 cites·36 claims
- 2198US6830964B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Dec 14, 2004·136 cites·76 claims
- 2297US7033437B2Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Apr 25, 2006·110 cites·28 claims
- 2397US6833294B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Dec 21, 2004·127 cites·28 claims
- 2496US7123792B1Configurable aperiodic grating deviceRJ MEARS LLC·Filed 2000·Granted Oct 17, 2006·128 cites·32 claims
- 2595US6878576B1Method for making semiconductor device including band-engineered superlatticeRJ MEARS LLC·Filed 2003·Granted Apr 12, 2005·117 cites·36 claims
- 2650US2007166928A1Method for making an electronic device including a selectively polable superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2750US2007158640A1Electronic device including a poled superlattice having a net electrical dipole momentRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2850US2007187667A1Electronic device including a selectively polable superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 2943US2006289049A1Semiconductor Device Having a Semiconductor-on-Insulator (SOI) Configuration and Including a Superlattice on a Thin Semiconductor LayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3041US2007063185A1Semiconductor device including a front side strained superlattice layer and a back side stress layerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3141US2007063186A1Method for making a semiconductor device including a front side strained superlattice layer and a back side stress layerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3240US2006292765A1Method for Making a FINFET Including a SuperlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3340US2007010040A1Method for Making a Semiconductor Device Including a Strained Superlattice Layer Above a Stress LayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3440US2006243964A1Method for making a semiconductor device having a semiconductor-on-insulator configuration and a superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3540US2007012910A1Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3640US2007020860A1Method for Making Semiconductor Device Including a Strained Superlattice and Overlying Stress Layer and Related MethodsRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3740US2006231857A1Method for making a semiconductor device including a memory cell with a negative differential resistance (ndr) deviceRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3840US2006223215A1Method for Making a Microelectromechanical Systems (MEMS) Device Including a SuperlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 3940US2007015344A1Method for Making a Semiconductor Device Including a Strained Superlattice Between at Least One Pair of Spaced Apart Stress RegionsRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 4040US2007020833A1Method for Making a Semiconductor Device Including a Channel with a Non-Semiconductor Layer MonolayerRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 4140US2006220118A1Semiconductor device including a dopant blocking superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 4240US2006267130A1Semiconductor Device Including Shallow Trench Isolation (STI) Regions with a Superlattice TherebetweenRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 4340US2006273299A1Method for making a semiconductor device including a dopant blocking superlatticeRJ MEARS LLC·Filed 2006·Application pending·0 cites
- 4439US2005279991A1Semiconductor device including a superlattice having at least one group of substantially undoped layersRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 4539US2005282330A1Method for making a semiconductor device including a superlattice having at least one group of substantially undoped layersRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 4638US2006011905A1Semiconductor device comprising a superlattice dielectric interface layerRJ MEARS LLC·Filed 2005·Application pending·0 cites
- 4736US2004262594A1Semiconductor structures having improved conductivity effective mass and methods for fabricating sameRJ MEARS LLC·Filed 2003·Application pending·0 cites
- 4836US2004266116A1Methods of fabricating semiconductor structures having improved conductivity effective massRJ MEARS LLC·Filed 2003·Application pending·0 cites
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