Assignee
NISHIMUDA KEIICHI
JP·2 granted patents·1 citations·filing 2011–2012
Technology mixH10W2
Top patents by PatentIndex Score
2 records- 0150US8418109B2Semiconductor integrated circuit with multi-cut via and automated layout method for the sameNISHIMUDA KEIICHI·Filed 2012·Granted Apr 9, 2013·1 cites·4 claims
- 0238US8271926B2Semiconductor integrated circuit with multi-cut via and automated layout method for the sameNISHIMUDA KEIICHI·Filed 2011·Granted Sep 18, 2012·0 cites·14 claims
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