Assignee
MEARS TECHNOLOGIES INC
US·27 granted patents·3 pending applications·3,023 citations·filing 2004–2014
Top patents by PatentIndex Score
30 records- 0199US7586165B2Microelectromechanical systems (MEMS) device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2006·Granted Sep 8, 2009·111 cites·14 claims
- 0299US7435988B2Semiconductor device including a MOSFET having a band-engineered superlattice with a semiconductor cap layer providing a channelMEARS TECHNOLOGIES INC·Filed 2005·Granted Oct 14, 2008·110 cites·37 claims
- 0399US7303948B2Semiconductor device including MOSFET having band-engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2005·Granted Dec 4, 2007·110 cites·11 claims
- 0498US7928425B2Semiconductor device including a metal-to-semiconductor superlattice interface layer and related methodsMEARS TECHNOLOGIES INC·Filed 2008·Granted Apr 19, 2011·113 cites·27 claims
- 0598US7880161B2Multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Feb 1, 2011·121 cites·25 claims
- 0698US7863066B2Method for making a multiple-wavelength opto-electronic device including a superlatticeMEARS TECHNOLOGIES INC·Filed 2007·Granted Jan 4, 2011·110 cites·25 claims
- 0798US7812339B2Method for making a semiconductor device including shallow trench isolation (STI) regions with maskless superlattice deposition following STI formation and related structuresMEARS TECHNOLOGIES INC·Filed 2008·Granted Oct 12, 2010·109 cites·23 claims
- 0898US7781827B2Semiconductor device with a vertical MOSFET including a superlattice and related methodsMEARS TECHNOLOGIES INC·Filed 2008·Granted Aug 24, 2010·136 cites·26 claims
- 0998US7718996B2Semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted May 18, 2010·110 cites·26 claims
- 1098US7700447B2Method for making a semiconductor device comprising a lattice matching layerMEARS TECHNOLOGIES INC·Filed 2007·Granted Apr 20, 2010·113 cites·28 claims
- 1198US7659539B2Semiconductor device including a floating gate memory cell with a superlattice channelMEARS TECHNOLOGIES INC·Filed 2006·Granted Feb 9, 2010·118 cites·17 claims
- 1298US7625767B2Methods of making spintronic devices with constrained spintronic dopantMEARS TECHNOLOGIES INC·Filed 2007·Granted Dec 1, 2009·117 cites·24 claims
- 1398US7612366B2Semiconductor device including a strained superlattice layer above a stress layerMEARS TECHNOLOGIES INC·Filed 2006·Granted Nov 3, 2009·120 cites·33 claims
- 1498US7598515B2Semiconductor device including a strained superlattice and overlying stress layer and related methodsMEARS TECHNOLOGIES INC·Filed 2006·Granted Oct 6, 2009·115 cites·15 claims
- 1598US7586116B2Semiconductor device having a semiconductor-on-insulator configuration and a superlatticeMEARS TECHNOLOGIES INC·Filed 2006·Granted Sep 8, 2009·111 cites·23 claims
- 1698US7531828B2Semiconductor device including a strained superlattice between at least one pair of spaced apart stress regionsMEARS TECHNOLOGIES INC·Filed 2006·Granted May 12, 2009·118 cites·27 claims
- 1798US7531829B2Semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistanceMEARS TECHNOLOGIES INC·Filed 2006·Granted May 12, 2009·114 cites·25 claims
- 1898US7531850B2Semiconductor device including a memory cell with a negative differential resistance (NDR) deviceMEARS TECHNOLOGIES INC·Filed 2006·Granted May 12, 2009·111 cites·24 claims
- 1998US7517702B2Method for making an electronic device including a poled superlattice having a net electrical dipole momentMEARS TECHNOLOGIES INC·Filed 2006·Granted Apr 14, 2009·130 cites·27 claims
- 2098US7514328B2Method for making a semiconductor device including shallow trench isolation (STI) regions with a superlattice therebetweenMEARS TECHNOLOGIES INC·Filed 2006·Granted Apr 7, 2009·123 cites·20 claims
- 2198US7491587B2Method for making a semiconductor device having a semiconductor-on-insulator (SOI) configuration and including a superlattice on a thin semiconductor layerMEARS TECHNOLOGIES INC·Filed 2006·Granted Feb 17, 2009·110 cites·21 claims
- 2298US7446002B2Method for making a semiconductor device comprising a superlattice dielectric interface layerMEARS TECHNOLOGIES INC·Filed 2005·Granted Nov 4, 2008·120 cites·21 claims
- 2398US7446334B2Electronic device comprising active optical devices with an energy band engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2004·Granted Nov 4, 2008·110 cites·25 claims
- 2498US7436026B2Semiconductor device comprising a superlattice channel vertically stepped above source and drain regionsMEARS TECHNOLOGIES INC·Filed 2004·Granted Oct 14, 2008·113 cites·45 claims
- 2598US7432524B2Integrated circuit comprising an active optical device having an energy band engineered superlatticeMEARS TECHNOLOGIES INC·Filed 2004·Granted Oct 7, 2008·111 cites·34 claims
- 2697US9275996B2Vertical semiconductor devices including superlattice punch through stop layer and related methodsMEARS TECHNOLOGIES INC·Filed 2014·Granted Mar 1, 2016·113 cites·10 claims
- 2793US7535041B2Method for making a semiconductor device including regions of band-engineered semiconductor superlattice to reduce device-on resistanceMEARS TECHNOLOGIES INC·Filed 2006·Granted May 19, 2009·26 cites·25 claims
- 2848US2010270535A1Electronic device including an electrically polled superlattice and related methodsMEARS TECHNOLOGIES INC·Filed 2010·Application pending·0 cites
- 2941US2008012004A1Spintronic devices with constrained spintronic dopantMEARS TECHNOLOGIES INC·Filed 2007·Application pending·0 cites
- 3039US2011215299A1Semiconductor device including a superlattice and dopant diffusion retarding implants and related methodsMEARS TECHNOLOGIES INC·Filed 2011·Application pending·0 cites
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