Assignee
MALLIK DEBENDRA
US·7 granted patents·3 pending applications·187 citations·filing 1988–2018
Top patents by PatentIndex Score
10 records- 0197US9210809B2Reduced PTH pad for enabling core routing and substrate layer count reductionMALLIK DEBENDRA·Filed 2013·Granted Dec 8, 2015·37 cites·13 claims
- 0294US9129958B23D integrated circuit package with window interposerMALLIK DEBENDRA·Filed 2011·Granted Sep 8, 2015·17 cites·24 claims
- 0393US4835120AMethod of making a multilayer molded plastic IC packageMALLIK DEBENDRA·Filed 1988·Granted May 30, 1989·118 cites·2 claims
- 0485US9530758B23D integrated circuit package with through-mold first level interconnectsMALLIK DEBENDRA·Filed 2015·Granted Dec 27, 2016·4 cites·16 claims
- 0583US8617990B2Reduced PTH pad for enabling core routing and substrate layer count reductionMALLIK DEBENDRA·Filed 2010·Granted Dec 31, 2013·5 cites·5 claims
- 0676US9099444B23D integrated circuit package with through-mold first level interconnectsMALLIK DEBENDRA·Filed 2011·Granted Aug 4, 2015·3 cites·22 claims
- 0771US9478476B2Package for a microelectronic die, microelectronic assembly containing same, microelectronic system, and method of reducing die stress in a microelectronic packageMALLIK DEBENDRA·Filed 2011·Granted Oct 25, 2016·3 cites·17 claims
- 0850US2015001732A1Silicon space transformer for ic packagingMALLIK DEBENDRA·Filed 2013·Application pending·0 cites
- 0939US2020098727A1Stacked wire-bond dice attached by pillars or bumps above a flip-chip die on a semiconductor package substrateMALLIK DEBENDRA·Filed 2018·Application pending·0 cites
- 1037US2013005162A1Multiple socket conceptMALLIK DEBENDRA·Filed 2011·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when MALLIK DEBENDRA files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →