Assignee
KOBAYASHI NAOHIRO
JP·5 granted patents·133 citations·filing 2008–2011
Top patents by PatentIndex Score
5 records- 0197US8239803B2Layout method and layout apparatus for semiconductor integrated circuitKOBAYASHI NAOHIRO·Filed 2011·Granted Aug 7, 2012·110 cites·7 claims
- 0285US8219965B2Layout design method of semiconductor integrated circuit including regenerating a cell layout to set first and second distances and generating library dataKOBAYASHI NAOHIRO·Filed 2011·Granted Jul 10, 2012·7 cites·9 claims
- 0380US8122386B2Dummy pattern placement apparatus, method and program and semiconductor deviceKOBAYASHI NAOHIRO·Filed 2008·Granted Feb 21, 2012·10 cites·1 claims
- 0473US8341560B2Method of designing semiconductor device including adjusting for gate antenna violationKOBAYASHI NAOHIRO·Filed 2010·Granted Dec 25, 2012·4 cites·20 claims
- 0564US8072078B2Semiconductor device and dummy pattern arrangement methodKOBAYASHI NAOHIRO·Filed 2009·Granted Dec 6, 2011·2 cites·8 claims
Join the waitlist — get patent alerts
Get an alert when KOBAYASHI NAOHIRO files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →