Assignee
IRIE KAZUYUKI
JP·3 granted patents·7 citations·filing 2009–2011
Top patents by PatentIndex Score
3 records- 0159US8164374B2Clock gating circuit having a selector that selects one of a control signal and a scan signalIRIE KAZUYUKI·Filed 2009·Granted Apr 24, 2012·4 cites·14 claims
- 0258US8312403B2Method of achieving convergence of hold time error, device and program thereforIRIE KAZUYUKI·Filed 2009·Granted Nov 13, 2012·2 cites·18 claims
- 0357US8751991B2Layout method, layout system, and non-transitory computer readable medium storing layout program of semiconductor integrated circuitIRIE KAZUYUKI·Filed 2011·Granted Jun 10, 2014·1 cites·23 claims
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