Assignee
INUI SHIGETO
JP·1 granted patent·1 pending application·1 citations·filing 2007–2011
Top patents by PatentIndex Score
2 records- 0143US8065645B2Logic circuit, logic circuit design method, logic circuit design system, and logic circuit design programINUI SHIGETO·Filed 2007·Granted Nov 22, 2011·1 cites·12 claims
- 0232US2012136599A1Wire verification method, wire verification apparatus and wire verification program for semiconductor integrated circuitINUI SHIGETO·Filed 2011·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →