Assignee
HSU FU CHANG
US·14 granted patents·18 pending applications·53 citations·filing 2009–2024
Top patents by PatentIndex Score
32 records- 0198US11049579B2Methods and apparatus for NAND flash memoryHSU FU CHANG·Filed 2020·Granted Jun 29, 2021·9 cites·19 claims
- 0289US8331150B2Integrated SRAM and FLOTOX EEPROM memory deviceHSU FU-CHANG·Filed 2009·Granted Dec 11, 2012·22 cites·90 claims
- 0383US10483324B23D vertical memory array cell structures and processesHSU FU CHANG·Filed 2016·Granted Nov 19, 2019·3 cites·6 claims
- 0481US11182664B2Configurable three-dimensional neural network arrayHSU FU CHANG·Filed 2018·Granted Nov 23, 2021·3 cites·17 claims
- 0579US8531885B2NAND-based 2T2b NOR flash array with a diode connection to cell's source node for size reduction using the least number of metal layersHSU FU-CHANG·Filed 2011·Granted Sep 10, 2013·5 cites·24 claims
- 0677US12029140B2Quantum bit arrayHSU FU CHANG·Filed 2023·Granted Jul 2, 2024·0 cites·8 claims
- 0775US10720215B2Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programmingHSU FU CHANG·Filed 2019·Granted Jul 21, 2020·3 cites·18 claims
- 0874US11205116B2Three-dimensional neural network arrayHSU FU CHANG·Filed 2017·Granted Dec 21, 2021·2 cites·20 claims
- 0973US8634254B2Single-polycrystalline silicon electrically erasable and programmable memory device of varied gate oxide thickness, using PIP or MIM coupling capacitor for cell size reduction and simultaneous VPP and VNN for write voltage reductionHSU FU-CHANG·Filed 2011·Granted Jan 21, 2014·5 cites·41 claims
- 1067US11723288B2Quantum bit arrayHSU FU CHANG·Filed 2021·Granted Aug 8, 2023·0 cites·20 claims
- 1167US2022083836A1Configurable Three-Dimensional Neural Network ArrayHSU FU CHANG·Filed 2021·Application pending·0 cites
- 1267US2024233821A93d cells and array structures and processesHSU FU CHANG·Filed 2023·Application pending·0 cites
- 1367US2024233822A93d memory cells and array structuresHSU FU CHANG·Filed 2023·Application pending·0 cites
- 1464US10840300B23D vertical memory array cell structures with individual selectors and processesHSU FU CHANG·Filed 2018·Granted Nov 17, 2020·1 cites·17 claims
- 1563US2024233823A93d array structures and processesHSU FU CHANG·Filed 2023·Application pending·0 cites
- 1663US2024147688A13d cells and array structuresHSU FU CHANG·Filed 2023·Application pending·0 cites
- 1762US11522016B23D vertical memory array cell structures with individual selectors and processesHSU FU CHANG·Filed 2020·Granted Dec 6, 2022·0 cites·6 claims
- 1860US10840301B23D vertical memory array cell structures with individual selectors and processesHSU FU CHANG·Filed 2019·Granted Nov 17, 2020·0 cites·16 claims
- 1960US2024306365A13d cell and array structures with parallel bit lines and source linesHSU FU CHANG·Filed 2024·Application pending·0 cites
- 2056US2022164638A1Methods and apparatus for neural network arraysHSU FU CHANG·Filed 2021·Application pending·0 cites
- 2156US2023154847A1Advanced structures having mosfet transistors and metal layersHSU FU CHANG·Filed 2022·Application pending·0 cites
- 2252US2021296360A1Three dimensional double-density memory arrayHSU FU CHANG·Filed 2021·Application pending·0 cites
- 2349US2022037519A1Transistor structures and associated processesHSU FU CHANG·Filed 2021·Application pending·0 cites
- 2447US10553293B23D NAND array with divided string architectureHSU FU CHANG·Filed 2018·Granted Feb 4, 2020·0 cites·13 claims
- 2547US2023106561A13d memory cells and array architecturesHSU FU CHANG·Filed 2022·Application pending·0 cites
- 2642US2019108437A1Two and three-dimensional neural network arraysHSU FU CHANG·Filed 2018·Application pending·0 cites
- 2742US2017133099A13d nand array with divided string architectureHSU FU-CHANG·Filed 2016·Application pending·0 cites
- 2841US2018174030A1Self-learning for neural network arraysHSU FU CHANG·Filed 2017·Application pending·0 cites
- 2941US2018157964A1High-density neural network arrayHSU FU CHANG·Filed 2017·Application pending·0 cites
- 3039US2017154926A13d cross-point array and process flowsHSU FU-CHANG·Filed 2016·Application pending·0 cites
- 3138US2017148812A1Methods and apparatus for a 3d array inside a substrate trenchHSU FU-CHANG·Filed 2016·Application pending·0 cites
- 3238US2019244666A1Methods and apparatus for memory cells that combine static ram and non volatile memoryHSU FU CHANG·Filed 2019·Application pending·0 cites
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