Assignee
CHAUDHRY SHAILENDER
US·8 granted patents·2 pending applications·7 citations·filing 2005–2012
Top patents by PatentIndex Score
10 records- 0166US8688963B2Checkpoint allocation in a speculative processorCHAUDHRY SHAILENDER·Filed 2010·Granted Apr 1, 2014·2 cites·20 claims
- 0265US8898436B2Method and structure for solving the evil-twin problemCHAUDHRY SHAILENDER·Filed 2009·Granted Nov 25, 2014·3 cites·20 claims
- 0364US8219831B2Reducing temperature and power by instruction throttling at decode stage of processor pipeline in time constant duration stepsCHAUDHRY SHAILENDER·Filed 2009·Granted Jul 10, 2012·2 cites·19 claims
- 0457US8745419B2Logical power throttling of instruction decode rate for successive time periodsCHAUDHRY SHAILENDER·Filed 2012·Granted Jun 3, 2014·0 cites·19 claims
- 0549US9256438B2Mechanism for increasing the effective capacity of the working register fileCHAUDHRY SHAILENDER·Filed 2009·Granted Feb 9, 2016·0 cites·20 claims
- 0649US2006271769A1Selectively deferring instructions issued in program order utilizing a checkpoint and instruction deferral schemeCHAUDHRY SHAILENDER·Filed 2006·Application pending·0 cites
- 0744US8447931B1Processor with a register file that supports multiple-issue executionCHAUDHRY SHAILENDER·Filed 2005·Granted May 21, 2013·0 cites·21 claims
- 0843US2007186081A1Supporting out-of-order issue in an execute-ahead processorCHAUDHRY SHAILENDER·Filed 2006·Application pending·0 cites
- 0942US8601240B2Selectively defering load instructions after encountering a store instruction with an unknown destination address during speculative executionCHAUDHRY SHAILENDER·Filed 2010·Granted Dec 3, 2013·0 cites·18 claims
- 1041US8627044B2Issuing instructions with unresolved data dependenciesCHAUDHRY SHAILENDER·Filed 2010·Granted Jan 7, 2014·0 cites·18 claims
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