Assignee
ATRENTA INC
US·38 granted patents·6 pending applications·313 citations·filing 2002–2015
Top patents by PatentIndex Score
44 records- 0187US8839171B1Method of global design closure at top level and driving of downstream implementation flowATRENTA INC·Filed 2013·Granted Sep 16, 2014·26 cites·20 claims
- 0285US8533647B1Method for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2012·Granted Sep 10, 2013·13 cites·12 claims
- 0384US8656326B1Sequential clock gating using net activity and XOR technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Feb 18, 2014·7 cites·6 claims
- 0483US7076748B2Identification and implementation of clock gating in the design of integrated circuitsATRENTA INC·Filed 2003·Granted Jul 11, 2006·47 cites·46 claims
- 0582US8930863B2System and method for altering circuit design hierarchy to optimize routing and power distribution using initial RTL-level circuit description netlistATRENTA INC·Filed 2013·Granted Jan 6, 2015·11 cites·22 claims
- 0682US8856706B2System and method for metastability verification of circuits of an integrated circuitATRENTA INC·Filed 2013·Granted Oct 7, 2014·7 cites·26 claims
- 0781US7650581B2Method for modeling and verifying timing exceptionsATRENTA INC·Filed 2007·Granted Jan 19, 2010·11 cites·19 claims
- 0880US7073146B2Method for clock synchronization validation in integrated circuit designATRENTA INC·Filed 2003·Granted Jul 4, 2006·30 cites·15 claims
- 0976US7536662B2Method for recognizing and verifying FIFO structures in integrated circuit designsATRENTA INC·Filed 2006·Granted May 19, 2009·11 cites·17 claims
- 1074US7451427B2Bus representation for efficient physical synthesis of integrated circuit designsATRENTA INC·Filed 2006·Granted Nov 11, 2008·7 cites·19 claims
- 1174US7152216B2Method, system, and computer program product for automatic insertion and correctness verification of level shifters in integrated circuits with multiple voltage domainsATRENTA INC·Filed 2004·Granted Dec 19, 2006·23 cites·36 claims
- 1273US8806401B1System and methods for reasonable functional verification of an integrated circuit designATRENTA INC·Filed 2013·Granted Aug 12, 2014·6 cites·27 claims
- 1373US7506292B2Method for clock synchronization validation in integrated circuit designATRENTA INC·Filed 2006·Granted Mar 17, 2009·6 cites·21 claims
- 1472US7941679B2Method for computing power savings and determining the preferred clock gating circuit of an integrated circuit designATRENTA INC·Filed 2007·Granted May 10, 2011·5 cites·22 claims
- 1571US8782582B1Efficient method to analyze RTL structures that cause physical implementation issues based on rule checking and overlap analysisATRENTA INC·Filed 2013·Granted Jul 15, 2014·4 cites·22 claims
- 1671US7546559B2Method of optimization of clock gating in integrated circuit designsATRENTA INC·Filed 2006·Granted Jun 9, 2009·6 cites·33 claims
- 1770US8863058B2Characterization based buffering and sizing for system performance optimizationATRENTA INC·Filed 2012·Granted Oct 14, 2014·5 cites·20 claims
- 1868US8732647B1Method for creating physical connections in 3D integrated circuitsATRENTA INC·Filed 2013·Granted May 20, 2014·4 cites·16 claims
- 1967US7712061B2Method, system, and computer program product for generating and verifying isolation logic modules in design of integrated circuitsATRENTA INC·Filed 2007·Granted May 4, 2010·4 cites·44 claims
- 2067US6993733B2Apparatus and method for handling of multi-level circuit design dataATRENTA INC·Filed 2002·Granted Jan 31, 2006·12 cites·119 claims
- 2165US8881075B2Method for measuring assertion density in a system of verifying integrated circuit designATRENTA INC·Filed 2013·Granted Nov 4, 2014·2 cites·14 claims
- 2265US8782587B2Systems and methods for generating a higher level description of a circuit design based on connectivity strengthsATRENTA INC·Filed 2012·Granted Jul 15, 2014·3 cites·10 claims
- 2365US8745567B1Efficient apparatus and method for analysis of RTL structures that cause physical congestionATRENTA INC·Filed 2013·Granted Jun 3, 2014·4 cites·19 claims
- 2464US8677295B1Sequential clock gating using net activity and xor technique on semiconductor designs including already gated pipeline designATRENTA INC·Filed 2013·Granted Mar 18, 2014·1 cites·5 claims
- 2564US8042085B2Method for compaction of timing exception pathsATRENTA INC·Filed 2008·Granted Oct 18, 2011·5 cites·16 claims
- 2664US7882483B2Method for checking constraints equivalence of an integrated circuit designATRENTA INC·Filed 2007·Granted Feb 1, 2011·5 cites·28 claims
- 2763US8756466B2Method and system thereof for optimization of power consumption of scan chains of an integrated circuit for testATRENTA INC·Filed 2013·Granted Jun 17, 2014·1 cites·7 claims
- 2863US7349835B2Method, system and computer program product for generating and verifying isolation logic modules in design of integrated circuitsATRENTA INC·Filed 2004·Granted Mar 25, 2008·10 cites·35 claims
- 2962US8984469B2System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Mar 17, 2015·1 cites·14 claims
- 3062US6876934B2Method for determining fault coverage from RTL descriptionATRENTA INC·Filed 2002·Granted Apr 5, 2005·14 cites·40 claims
- 3161US8635578B1System and method for strengthening of a circuit element to reduce an integrated circuit's power consumptionATRENTA INC·Filed 2013·Granted Jan 21, 2014·1 cites·11 claims
- 3259US7216321B2Pattern recognition in an integrated circuit designATRENTA INC·Filed 2004·Granted May 8, 2007·11 cites·37 claims
- 3358US8788993B2Computer system for generating an integrated and unified view of IP-cores for hierarchical analysis of a system on chip (SoC) designATRENTA INC·Filed 2013·Granted Jul 22, 2014·1 cites·12 claims
- 3455US7277840B2Method for detecting bus contention from RTL descriptionATRENTA INC·Filed 2002·Granted Oct 2, 2007·9 cites·45 claims
- 3550US8813003B2System and method for inferring higher level descriptions from RTL topology based on naming similarities and dependencyATRENTA INC·Filed 2013·Granted Aug 19, 2014·0 cites·17 claims
- 3648US8984457B2System and method for a hybrid clock domain crossing verificationATRENTA INC·Filed 2013·Granted Mar 17, 2015·0 cites·17 claims
- 3743US8656328B1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2013·Granted Feb 18, 2014·0 cites·28 claims
- 3843US2014282322A1System and method for filtration of error reports respective of static and quasi-static signals within an integrated circuit designATRENTA INC·Filed 2013·Application pending·0 cites
- 3942US8739087B1System and method for large multiplexer identification and creation in a design of an integrated circuitATRENTA INC·Filed 2013·Granted May 27, 2014·0 cites·19 claims
- 4040US2015234973A1System and method for abstraction of a circuit portion of an integrated circuitATRENTA INC·Filed 2014·Application pending·0 cites
- 4139US2008201671A1Method for generating timing exceptionsATRENTA INC·Filed 2007·Application pending·0 cites
- 4238US2008244472A1Method for accelerating the generation of an optimized gate-level representation from a rtl representationATRENTA INC·Filed 2007·Application pending·0 cites
- 4337US2006190754A1A Method for Automatic Recognition of Handshake Data Exchange at Clock-Domain Crossing in Integrated Circuit DesignATRENTA INC·Filed 2005·Application pending·0 cites
- 4435US2015379186A1System and method for grading and selecting simulation tests using property coverageATRENTA INC·Filed 2015·Application pending·0 cites
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