Assignee
SYNTHESYS RES INC
US·12 granted patents·92 citations·filing 2002–2007
Top patents by PatentIndex Score
12 records- 0185US7642767B2Method and apparatus for measuring duty cycleSYNTHESYS RES INC·Filed 2006·Granted Jan 5, 2010·16 cites·18 claims
- 0282US7363562B2Method and apparatus for deferred decision signal quality analysisSYNTHESYS RES INC·Filed 2005·Granted Apr 22, 2008·20 cites·9 claims
- 0375US7643599B2Method and apparatus for detecting linear phase errorSYNTHESYS RES INC·Filed 2006·Granted Jan 5, 2010·7 cites·11 claims
- 0466US7062733B1Method and apparatus for delay line calibrationSYNTHESYS RES INC·Filed 2002·Granted Jun 13, 2006·18 cites·36 claims
- 0563US7606297B2Method and system for creating an eye diagram using a binary data bit decision mechanismSYNTHESYS RES INC·Filed 2002·Granted Oct 20, 2009·11 cites·30 claims
- 0663US7386405B2Apparatus and method for sampling eye diagrams with window comparatorsSYNTHESYS RES INC·Filed 2006·Granted Jun 10, 2008·2 cites·13 claims
- 0760US7477078B2Variable phase bit sampling with minimized synchronization lossSYNTHESYS RES INC·Filed 2005·Granted Jan 13, 2009·3 cites·8 claims
- 0858US7788571B2Method and apparatus for using dual bit decisions to measure bit errors and event occurrencesSYNTHESYS RES INC·Filed 2004·Granted Aug 31, 2010·8 cites·14 claims
- 0953US7301325B2Method and apparatus for creating performance limits from parametric measurementsSYNTHESYS RES INC·Filed 2005·Granted Nov 27, 2007·2 cites·17 claims
- 1051US7467336B2Method and apparatus to measure and display data dependent eye diagramsSYNTHESYS RES INC·Filed 2005·Granted Dec 16, 2008·2 cites·13 claims
- 1150US7298220B2Method and apparatus for creating a multiple loop VCOSYNTHESYS RES INC·Filed 2006·Granted Nov 20, 2007·2 cites·5 claims
- 1242US7712014B2Synchronizing clock and aligning signals for testing electronic devicesSYNTHESYS RES INC·Filed 2007·Granted May 4, 2010·1 cites·11 claims
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