Assignee
SCHAEFER ANDRE
DE·7 granted patents·3 pending applications·42 citations·filing 2005–2014
Top patents by PatentIndex Score
10 records- 0188US8135936B2Adaptive address mapping with dynamic runtime memory mapping selectionSCHAEFER ANDRE·Filed 2009·Granted Mar 13, 2012·20 cites·19 claims
- 0281US9230614B2Separate microchannel voltage domains in stacked memory architectureSCHAEFER ANDRE·Filed 2011·Granted Jan 5, 2016·6 cites·24 claims
- 0380US9026767B2Adaptive address mapping with dynamic runtime memory mapping selectionSCHAEFER ANDRE·Filed 2012·Granted May 5, 2015·6 cites·21 claims
- 0480US8811110B2Configuration for power reduction in DRAMSCHAEFER ANDRE·Filed 2012·Granted Aug 19, 2014·6 cites·9 claims
- 0574US8418610B2Printing unitSCHAEFER ANDRE·Filed 2009·Granted Apr 16, 2013·2 cites·10 claims
- 0658US8321719B2Efficient clocking scheme for a bidirectional data linkSCHAEFER ANDRE·Filed 2009·Granted Nov 27, 2012·1 cites·15 claims
- 0755US9311983B2Dynamically applying refresh overcharge voltage to extend refresh cycle timeSCHAEFER ANDRE·Filed 2014·Granted Apr 12, 2016·1 cites·20 claims
- 0840US2006049511A1Integrated semiconductor circuit and method for producing an integrated semiconductor circuitSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
- 0933US2006152957A1Circuit arrangement and method for setting operating parameters in a RAM moduleSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
- 1033US2006085705A1Memory circuit comprising an initialization unit, and method for optimizing data reception parameters in a memory controllerSCHAEFER ANDRE·Filed 2005·Application pending·0 cites
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