Assignee
LEE JONG-JOO
KR·19 granted patents·2 pending applications·73 citations·filing 2006–2017
Top patents by PatentIndex Score
21 records- 0195US8471362B2Three-dimensional stacked structure semiconductor device having through-silicon via and signaling method for the semiconductor deviceLEE JONG-JOO·Filed 2011·Granted Jun 25, 2013·25 cites·18 claims
- 0291US9391048B2Semiconductor packageLEE JONG-JOO·Filed 2014·Granted Jul 12, 2016·12 cites·25 claims
- 0386US8319351B2Planar multi semiconductor chip packageLEE JONG-JOO·Filed 2010·Granted Nov 27, 2012·7 cites·26 claims
- 0481US8643178B2Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the sameLEE JONG-JOO·Filed 2013·Granted Feb 4, 2014·5 cites·12 claims
- 0576USRE46666EPackage board having internal terminal interconnection and semiconductor package employing the sameLEE JONG-JOO·Filed 2014·Granted Jan 9, 2018·3 cites·72 claims
- 0675US8125068B2Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chipLEE JONG-JOO·Filed 2009·Granted Feb 28, 2012·5 cites·16 claims
- 0773US8625938B2Electronic device having optical communicating partLEE JONG-JOO·Filed 2012·Granted Jan 7, 2014·3 cites·20 claims
- 0870US8604616B2Semiconductor chip including a chip via plug penetrating a substrate, a semiconductor stack, a semiconductor device package and an electronic apparatus including the semiconductor chipLEE JONG-JOO·Filed 2012·Granted Dec 10, 2013·2 cites·15 claims
- 0969US8410611B2Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the sameLEE JONG-JOO·Filed 2012·Granted Apr 2, 2013·1 cites·20 claims
- 1068US8853854B2Semiconductor package and method of manufacturing the sameLEE JONG-JOO·Filed 2011·Granted Oct 7, 2014·2 cites·17 claims
- 1168US8796847B2Package substrate having main dummy pattern located in path of stressLEE JONG-JOO·Filed 2011·Granted Aug 5, 2014·2 cites·18 claims
- 1266US8309372B2Method of manufacturing stacked semiconductor packageLEE JONG-JOO·Filed 2011·Granted Nov 13, 2012·2 cites·10 claims
- 1365US8115315B2Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the sameLEE JONG-JOO·Filed 2009·Granted Feb 14, 2012·1 cites·21 claims
- 1464US8178969B2Flip chip packageLEE JONG-JOO·Filed 2009·Granted May 15, 2012·2 cites·19 claims
- 1554US10128191B2Package-on-package type package including integrated circuit devices and associated passive components on different levelsLEE JONG JOO·Filed 2017·Granted Nov 13, 2018·0 cites·20 claims
- 1652US9679853B2Package-on-package type package including integrated circuit devices and associated passive components on different levelsLEE JONG-JOO·Filed 2013·Granted Jun 13, 2017·0 cites·13 claims
- 1752US8723315B2Flip chip packageLEE JONG-JOO·Filed 2012·Granted May 13, 2014·0 cites·14 claims
- 1852US8061024B2Method of fabricating a circuit board and semiconductor package.LEE JONG-JOO·Filed 2008·Granted Nov 22, 2011·1 cites·20 claims
- 1948US8319324B2High I/O semiconductor chip package and method of manufacturing the sameLEE JONG-JOO·Filed 2007·Granted Nov 27, 2012·0 cites·27 claims
- 2048US2009230520A1Leadframe package with dual lead configurationsLEE JONG-JOO·Filed 2009·Application pending·0 cites
- 2142US2007029662A1Semiconductor device having termination circuit lineLEE JONG-JOO·Filed 2006·Application pending·0 cites
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Counts cover granted patents and pending applications in the PatentIndex corpus. How scoring works →