Assignee
BHARDWAJ VIVEK
IN·4 granted patents·57 citations·filing 2009–2013
Technology mixG06F4
Top patents by PatentIndex Score
4 records- 0191US8935642B1Methods for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Jan 13, 2015·13 cites·15 claims
- 0291US8539402B1Systems for single pass parallel hierarchical timing closure of integrated circuit designsBHARDWAJ VIVEK·Filed 2012·Granted Sep 17, 2013·13 cites·5 claims
- 0387US8504978B1User interface for timing budget analysis of integrated circuit designsBHARDWAJ VIVEK·Filed 2009·Granted Aug 6, 2013·23 cites·29 claims
- 0483US8745560B1Methods for generating a user interface for timing budget analysis of integrated circuit designsBHARDWAJ VIVEK·Filed 2013·Granted Jun 3, 2014·8 cites·26 claims
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