System and method for instruction-level parallelism in a programmable multiple network processor environment

Abstract

A system and method process data elements with instruction-level parallelism. An instruction buffer holds a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread. A dependency counter counts satisfaction of dependencies of instructions of the second thread on instructions of the first thread. An instruction control unit is coupled to the instruction buffer and the dependency counter, the instruction control unit increments and decrements the dependency counter according to dependency information included in instructions. An execution switch is coupled to the instruction control unit and the instruction buffer, and the execution switch routes instructions to instruction execution units.

What is claimed is: 
     
       1. An apparatus for instruction-level parallelism in a processing element, comprising: an instruction control unit; The apparatus of claim 7, wherein the instruction buffer comprises:
 a first instruction buffer coupled to said instruction control unit, the first instruction buffer configured to hold a the first instructionincluding a dependency indicator and being associated with a first thread;, and  
 a second instruction buffer coupled to said instruction control unit, the second instruction buffer configured to hold a the second instructionincluding a dependency indicator and being associated with a second thread; a dependency counter coupled to said instruction control unit;; and wherein  
 anthe execution switch is coupled to said instruction control unit, said first instruction buffer, and said second instruction buffer; and 
 an execution unit coupled to said execution switch; 
 said instruction control unit configured to detect the dependency indicators and change the value of said dependency counter in response to detecting the dependency indicators and configured to disallow execution of the first instruction if said dependency counter includes a value less than a threshold value. 
 
     
     
       2. The apparatus of  claim 1 , wherein said dependency counter includes a first counter associated with the first instruction buffer and a second counter associated with the second instruction buffer. 
     
     
       3. The apparatus of  claim 1 , wherein said instruction control unit identifies instruction dependency bits in said first instruction buffer, the instruction dependency bits being associated with instructions. 
     
     
       4. The apparatus of  claim 1 , said instruction control unit generating control signals based on the dependency bits and values included in said dependency counter. 
     
     
       5. The apparatus of  claim 4 , said execution switch providing instructions from said first instruction buffer to said execution unit based on control signals from said instruction control unit. 
     
     
       6. The apparatus of  claim 1 , said execution switch providing instructions from said first instruction buffer to said execution unit based on control signals from said instruction control unit. 
     
     
       7. An apparatus for processing instructions in multiple threads in an execution unit, comprising:
 an instruction buffer holding configured to hold a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread, the first instruction and the second instruction including one or more instruction dependency bits; 
 a dependency counter, 
 an instruction control unit coupled to said instruction buffer and said dependency counter, said instruction control unit detecting configured to detect the instruction dependency bits and incrementing and decrementing to increment and decrement said dependency counter in response to detecting the instruction dependence bits, said instruction control unit configured to disallow execution of the first instruction if in response to said dependency counter includes including a value less than a threshold value; and 
 an execution switch coupled to said instruction control unit and said instruction buffer, said execution switch sending configured to send instructions to the execution unit. 
 
     
     
       8. The apparatus of  claim 7 , wherein said dependency counter includes a first counter associated with the first thread and a second counter associated with the second thread. 
     
     
       9. The apparatus of  claim 7 , wherein said instruction buffer includes the instruction dependency bits, the instruction dependency bits being associated with instructions. 
     
     
       10. The apparatus of  claim 7 , wherein said instruction control detects dependency between the first instruction and the second thread based on dependency bits in said instruction buffer and a value of said dependency counter. 
     
     
       11. A method for processing instructions in multiple threads, comprising:
 receiving a first instruction associated with a first thread; 
 determining whether execution of the first instruction depends on execution of a second instruction, the second instruction being associated with a second thread; 
 examining a counter logic element associated with the first thread if in response to said determining indicates indicating that the first instruction depends on the execution of the second instruction, wherein the logic element comprises a single bi-state element or a tri-state element; 
 decrementing the counter ifmodifying the logic element in response to said examining indicatesindicating that the second instruction has already been executed; and 
 executing the first instruction; and 
 suspending the processing of the first thread until said examining indicates that the second instruction has already been executed and then resuming processing. 
 
     
     
       12. The method of  claim 11 , further comprising suspending the processing of the first thread until said examining indicates that the second instruction has already been executed. 
     
     
       13. A method for processing instructions in multiple threads, comprising:
 receiving a first instruction associated with a first thread; 
 determining whether execution of a second instruction depends on the execution of the first instruction, the second instruction being associated with a second thread; 
 incrementing a counter associated with the second thread if in response to said determining indicates indicating that execution of a second instruction depends on the execution of the first instruction; and 
 executing the first instruction; and 
 suspending the processing of the second thread in response to the counter associated with the second thread not exceeding a threshold and resuming the processing of the second thread in response to the counter associated with the second thread exceeding the threshold; 
 wherein the first instruction and the second instruction include one or more instruction dependency bits. 
 
     
     
       14. The method of  claim 13 , further comprising suspending the processing of the second thread if the counter associated with the second thread does not exceed a threshold. 
     
     
       15. A method for processing instructions in multiple threads, comprising:
 receiving a first instruction associated with a first thread, the first instruction including one or more instruction dependency bits; 
 determining whether a second thread depends on said first instruction; 
 incrementing a counter associated with the second thread if in response to the second thread depends depending on said first instruction; 
 loading a second instruction associated with a second thread; and 
 processing the second instruction in a manner related to the value of the counter associated with the second thread; and 
 suspending, the processing of the second thread in response to the counter not exceeding a threshold and resuming the processing of the second thread in response to the counter exceeding said threshold. 
 
     
     
       16. The method of  claim 15 , further comprising suspending the processing the second thread if the counter indicates that a dependent thread has not been executed. 
     
     
       17. The method of  claim 15 , further comprising executing the second instruction if the counter indicates that said first instruction has been executed. 
     
     
       18. An apparatus for processing instructions in multiple threads, comprising:
 an instruction buffer configured to hold a first instruction and a second instruction, the first instruction including a dependency indicator and being associated with a first thread, and the second instruction including a dependency indicator and being associated with a second thread; 
 an instruction control unit coupled to said instruction buffer; 
 a dependency counter coupled to said instruction control unit, said dependency counter associated with the first thread; 
 said instruction control unit configured to detect the dependency indicators and change the value of increment and decrement said dependency counter in response to detecting the dependency indicators; and 
 said instruction control unit configured to disallow execution of the first instruction if in response to said dependency counter includes including a value less than a threshold value. 
 
     
     
       19. The apparatus of  claim 18 , wherein said instruction control unit is configured to determine that the dependency indicator included in the first instruction indicates that the second thread includes an instruction on which the first instruction depends. 
     
     
       20. The apparatus of  claim 18 , wherein the dependency indicator included in the first instruction is a depends bit. 
     
     
       21. The apparatus of  claim 18 , wherein said instruction control unit is configured to determine that the dependency indicator included in the second instruction indicates that the first thread includes an instruction that is dependent on the second instruction. 
     
     
       22. The apparatus of  claim 18 , wherein the dependency indicator included in the second instruction is a tells bit. 
     
     
       23. The apparatus of claim  18  25, wherein said instruction control unit is configured to increment said dependency counter in response to detecting the dependency indicator included in the second instruction. 
     
     
       24. The apparatus of claim  18  25, wherein said instruction control unit is configured to decrement said dependency counter in response to detecting the dependency indicator included in the first instruction. 
     
     
       25. The apparatus according to claim 18, wherein said dependency counter is coupled to said instruction control unit and associated with the first thread. 
     
     
       26. A method for processing instructions in multiple threads, comprising:
 receiving a first instruction associated with a first thread;   determining that execution of the first instruction depends on execution of a second instruction, the second instruction being associated with a second thread;   examining a dependency counter associated with the first thread to determine whether the second instruction has already been executed;   incrementing the dependency counter in response to said determining indicating that execution of the first instruction depends on execution of the second instruction; and   suspending the processing of the first thread when examining indicates that the dependency counter does not exceed a threshold and resuming the processing after the dependency counter exceeds said threshold,   wherein the first instruction and the second instruction include one or more instruction dependency bits.