USRE37195EExpiredUtilityPatentIndex 99
Programmable switch for FPGA input/output signals
Est. expiryMay 2, 2015(expired)· nominal 20-yr term from priority
Inventors:KEAN THOMAS A
H03K 19/17744H03K 19/17704H03K 19/17756H03K 19/1778H03K 19/17788H03K 19/17772
99
PatentIndex Score
158
Cited by
11
References
59
Claims
Abstract
A programmable switch for a field programmable gate array (FPGA) allows a user to reconfigure or partly reconfigure the FPGA from within the FPGA, allows an addressable configuration memory to be addressed through a set of pins for configuration and through user logic for reconfiguration. The same pins can be used for both configuration and user logic. Also signals such as chip enable and other control signals can be modified by user logic before performing their function so that chips external to the FPGA can be eliminated. Upon power-up of the chip, each programmable switch connects its pad to the programming logic which programs configuration memory, so that the programming logic can receive instructions from an external source and control programming of the core logic of the chip. The configuration memory programs not only the internal circuitry accessed by the user but also the programmable switch itself. Thus as configuration proceeds, or after configuration is completed, the programmable switch can be reconfigured to connect internal portions of the FPGA user logic to parts of the configuration memory which were initially loaded from external pins.
Claims
exact text as granted — not AI-modifiedI claim:
1. A programmable logic device comprising:
a user logic structure;
a configuration memory for controlling said user logic structure;
structure for accessing said configuration memory;
a plurality of pads for connecting external signals to said programmable logic device;
a programmable switch, said programmable switch being programmable to connect signals between said pads, said user logic structure, and said structure for accessing said configuration memory, said programmable switch being programmed by said configuration memory.
2. A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from one of said pads and a signal from said user logic structure and provides as output a signal to said structure for accessing said configuration memory.
3. A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from said user logic structure and a signal from said structure for accessing said configuration memory and provides as an output a signal to one of said pads.
4. A programmable logic device as in claim 3 in which said signal to one of said pads is programmably provided to said pad in response to an enable signal derived from said user logic structure and said structure for accessing said configuration memory.
5. A programmable logic device as in claim 3 in which said signal to one of said pads is programmably provided to said pad in response to an enable signal derived from said user logic structure.
6. A programmable logic device as in claim 1 in which said programmable switch includes a multiplexer which receives as input signals a signal from said user logic structure and a signal from one of said pads and provides as output a signal to said user logic structure.
7. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from said pads and providing one or more output signals to one or more of said pads;
a configurable memory for configuring said user logic portion; and
a switch for coupling at least one output signal from said user logic portion to said configuration memory so that said output signal can be stored in said configuration memory.
8. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from and providing one or more output signals to said pads;
a configuration memory for configuring said user logic portion;
circuitry for receiving control signals and data signals and storing said data signals in said configuration memory in response to said control signals; and
a switch for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.
9. Programmable logic device of claim 8 wherein said control signal is an address signal.
10. Programmable logic device of claim 8 wherein said control signal controls whether data is to be written to or read from said configuration memory.
11. Programmable logic device of claim 8 wherein said control signal is an enable signal for said configuration memory.
12. Programmable logic device of claim 8 wherein said programmable logic device is incorporated into a system comprising a processor said processor providing address signals to said user logic, said user logic asserting a chip select function signal to said configuration memory in response to said address signals.
13. Programmable logic device of claim 8 wherein said programmable logic device receives a control signal from a source external to said programmable logic device and provides said control signal to said user logic portion, said user logic portion modifying said control signal and applying said modified control signal to said configuration memory.
14. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from and providing one or more output signals to said pads;
a configuration memory for configuring said user logic portion;
circuitry for receiving control signals and providing data signals from said configuration memory in response to said control signals; and
a switch for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.
15. Programmable logic device of claim 14 wherein said control signal is an address signal.
16. Programmable logic device of claim 14 wherein said control signal controls whether data is to be written to or read from said configuration memory.
17. Programmable logic device of claim 14 wherein said control signal is an enable signal for said configuration memory.
18. Programmable logic device of claim 14 wherein said programmable logic device is incorporated into a system comprising a processor, said processor providing address signals to said user logic, said user logic asserting a chip select function signal to said configuration memory in response to said address signals.
19. Programmable logic device of claim 14 wherein said programmable logic device receives a control signal from a source external to said programmable logic device and provides said control signal to said user logic portion, said user logic portion modifying said control signal and applying said modified control signal to said configuration memory.
20. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from said pads and for providing one or more output signals on said pads;
a configuration memory for configuring said user logic portion;
a switch for receiving a first output signal from said configuration memory and a second output signal from said user logic portion and providing said first or second output signals to one of said pads, said switch being controlled by a third output signal from said user logic portion.
21. A programmable logic device comprising:
a user logic portion for performing selected logic functions;
a configuration memory for controlling the functions performed by said user logic portion;
a set of pads for receiving signals from an external source, at least some of said signals comprising data signals to be stored in said configuration memory; and
circuitry for selecting locations within said configuration memory for receiving said data signals, said locations being selected in part by said user logic portion.
22. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving signals from said pads and providing one or more output signals on one or more of said pads;
a configuration memory for controlling the function performed by said user logic portion, said user logic portion detecting the presence of selected data received on said pads and copying configuration data from one portion of said configuration memory into another portion of said configuration memory in response to the presence of said selected data.
23. A programmable logic device comprising:
a user logic portion;
a configuration memory for controlling the function performed by said user logic portion;
circuitry for receiving configuration data and storing said configuration data within said configuration memory, said circuitry comprising a switch, said switch being controlled by configuration data already received by said programmable logic device and controlling where within said configuration memory additional configuration data is to be stored.
24. A programmable logic device comprising:
a user logic portion;
a configuration memory for controlling the function performed by said user logic portion;
circuitry for receiving configuration data and storing said configuration data within said configuration memory, said user logic portion monitoring said configuration data and initiating an action in response to a predetermined pattern of data bits.
25. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from said pads and providing one or more output signals to one or more of said pads;
a configurable memory for configuring said user logic portion; and
means for coupling at least one output signal from said user logic portion to said configuration memory so that said output signal can be stored in said configuration memory.
26. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from and providing one or more output signals to said pads;
a configuration memory for configuring said user logic portion;
circuitry for receiving control signals and data signals and storing said data signals in said configuration memory in response to said control signals; and
means for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.
27. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from and providing one or more output signals to said pads;
a configuration memory for configuring said user logic portion;
circuitry for receiving control signals and providing data signals from said configuration memory in response to said control signals; and
means for receiving an output signal from said user logic portion and applying said output signal as a control signal to said circuitry for receiving.
28. A programmable logic device comprising:
a set of pads for receiving signals from a source external to the programmable logic device or providing signals to a destination external to the programmable logic device;
a user logic portion for receiving input signals from said pads and for providing one or more output signals on said pads;
a configuration memory for configuring said user logic portion;
means for receiving a first output signal from said configuration memory and a second output signal from said user logic portion and providing said first or second output signals to one of said pads, said means for receiving being controlled by a third output signal from said user logic portion.
29. A programmable logic device comprising:
a user logic portion for performing selected logic functions;
a configuration memory for controlling the functions performed by said user logic portion;
a set of pads for receiving signals from an external source, at least some of said signals comprising data signals to be stored in said configuration memory; and
means for selecting locations within said configuration memory for receiving said data signals, said locations being selected in part by said user logic portion.
30. A programmable logic device comprising:
a user logic portion;
a configuration memory for controlling the function performed by said user logic portion;
circuitry for receiving configuration data and storing said configuration data within said configuration memory, said circuitry comprising means controlled by configuration data already received by said programmable logic device for controlling where within said configuration memory additional configuration data is to be stored.
31. A programmable logic device comprising:
a user logic structure;
a configuration memory for controlling said user logic structure;
a structure for accessing said configuration memory;
a plurality of pads for connecting external signals to said programmable logic device;
means for connecting signals between said pads, said user logic structure, and said structure for accessing said configuration memory, said means for connecting being controlled by said configuration memory.
32. In a programmable logic device comprising:
a ) a user logic section having user memory devices;
b ) a configuration memory comprising a set of memory cells for storing configuration data and for controlling the function performed by the user logic; and
c ) a configuration memory interface circuit for loading data into or reading data out of said configuration memory,
a method for swapping data in and out of a configurable logic device comprising:
a ) using said configuration memory interface for reading data stored in said user memory devices; and
b ) using said configuration memory interface for writing new data into said user memory devices.
33. Method of claim 32 further comprising using said configuration memory interface for writing new configuration data into said configuration memory.
34. Method of claim 33 further comprising using said configuration memory interface for reading configuration data stored in said configuration memory prior to writing new configuration data into said configuration memory.
35. Method of claim 32 wherein said programmable logic device comprises a clock line for clocking said user memory devices, said method further comprising:
preventing clock signals from appearing on said clock line prior to said reading data stored in said user memory devices so that said data in said user memory devices cannot be changed by said user logic section.
36. Method of claim 32 wherein said programmable logic device comprises a set of register protect memory cells for generating a signal that prevents the user logic section from writing data to said user memory devices, said programmable logic device also comprising a clock line for clocking said user memory devices, said method comprising:
storing a value in said register protect memory cells for generating said signal that prevents the user logic section from writing data to said user memory devices, said storing being performed prior to said writing new data.
37. Method of claim 36 wherein said configuration memory comprises a set of bit lines, each of said bit lines being coupled to an associated set of memory cells within said configuration memory, each of said bit lines also being coupled to an associated set of user memory devices, wherein during said using of said configuration memory interface to write data into said user memory devices, data is communicated from said bit lines into said associated user memory devices.
38. Method of claim 32 wherein said configuration memory interface comprises address decoders for decoding an address and selecting memory cells within said configuration memory, said decoders also selecting user memory devices so that data can be used to write data into or out of selected user memory devices.
39. A programmable logic device comprising:
a programmable user logic portion for performing selected logic functions, said programmable logic user portion comprising a set of user memory cells for storing user logic signals;
a configuration memory section comprising a set of configuration memory cells, the data stored in said configuration memory section controlling the logic function performed by said user logic portion; and
a configuration memory interface for writing data to said configuration memory cells, said configuration memory interface also being coupled to said user memory cells said configuration memory interface being used to read data from said user memory cells and to write data to said user memory cells.
40. Programmable logic device of claim 39 further comprising:
a set of register protect memory cells for generating a signal that prevents said programmable user logic portion from writing data to said user memory cells when said configuration memory interface writes data into said user memory cells.
41. Programmable logic device of claim 39 wherein said configuration memory interface comprises a set of decoders for selecting memory cells within said configuration memory section, said decoders also selecting user memory cells when said configuration memory interface writes data into said user memory cells.
42. Programmable logic device of claim 39 further comprising:
a clock line for providing a clock signal to said user memory cells; and
means for preventing clock signals from appearing on said user memory cells so that data being read from said user memory cells by said configuration memory interface are not altered by said user logic portion during reading of said user memory cells.
43. Programmable logic device comprising:
a programmable user logic portion for performing selected logic functions, said user logic portion comprising user memory cells for storing user logic signals;
a configuration memory for controlling the function performed by said programmable user logic portion;
a set of input/output pads;
configuration memory interface means for receiving data from said input/output pads and storing data in said configuration memory, said configuration memory interface means also storing data in and reading data from said user memory cells.
44. In a circuit comprising a) at least one bit line; b ) a set of memory cells; and c ) a set of switches for coupling said memory cells to said bit line, a method for setting said memory cells to a logic value comprising:
applying a signal on said bit line, said signal corresponding to said logic value;
coupling a first subset of said memory cells to said bit line, whereby said first subset of memory cells are set to said logic value; and
thereafter coupling a second subset of memory cells to said bit line while said first subset of memory cells are coupled to said bit line, whereby said second subset of memory cells are set to said logic value.
45. Method of claim 44 wherein said applying of said signal to said bit line is accomplished using a driver circuit, and coupling said second subset of said memory cells to said bit line after said coupling of said first subset of said memory cells to said bit line prevents said first and second subsets of memory cells from overpowering said driver.
46. Structure comprising:
a bit line;
a driver for applying a value to said bit line;
a set of memory cells;
a set of switches for coupling said set of memory cells to said bit line, said driver setting said memory cells to an initial value, wherein when said driver sets said memory cells to said initial value, a first subset of switches within said set of switches closes to couple a first subset of memory cells within said set of memory cells to said bit line to set said first subset of memory cells to said initial value, and thereafter a second subset of switches within said set of switches closes to couple a second subset of memory cells within said set of memory cells to said bit lines to set said second subset of memory cells to said initial value.
47. Structure comprising:
a bit line;
a driver for applying a value to said bit line;
a set of memory cells;
switch means for coupling said set of memory cells to said bit line, said driver setting said memory cells to an initial value, wherein when said driver sets said memory cells to said initial value, said switch means couples a first subset of memory cells within said set of memory cells to said bit line to set said first subset of memory cells to said initial value, and thereafter said switch means couples a second subset of memory cells within said set of memory cells to said bit lines to set said second subset of memory cells to said initial value.
48. In a system comprising a configuration data source and a programmable logic device, and said programmable logic device comprising a register storing identifying data, a method comprising:
having said configuration data source read said identifying data in said register within said programmable logic device; and
causing said configuration data source to configure said programmable logic device by providing configuration data to said programmable logic device, said configuration data being selected in response to said identifying data.
49. Method of claim 48 wherein said configuration data source comprises a host processor.
50. In a system comprising a configuration data source and a programmable logic device, a method comprising:
causing said configuration data source to provide configuration data to said programmable logic device;
causing said programmable logic device to analyze a portion of said configuration data, and if said portion comprises a first value, using said configuration data to configure said programmable logic device, and if said portion comprises a second value, disabling the output buffers of said programmable logic device.
51. Method of claim 50 wherein said configuration data source is a host processor.
52. In a system comprising a configuration data source and a programmable logic device, a method comprising:
causing said configuration data source to provide configuration data to said programmable logic device;
causing said programmable logic device to analyze a portion of said configuration data, and if said portion comprises a first value, using said configuration data to configure said programmable logic device with said configuration data, and if said portion comprises a second value, not configuring said programmable logic device with said configuration data.
53. In a system comprising a programmable logic device, a method comprising:
providing configuration data to said programmable logic device;
causing said programmable logic device to analyze a portion of said configuration data, and if said portion comprises a first value, using said configuration data to configure said programmable logic device to behave as a first device type, and if said portion comprises a second value, using said configuration data to configure said programmable logic device to behave as a second device type.
54. A system comprising:
a configuration data source;
a programmable logic device for receiving said configuration data from said configuration data source, said programmable logic device containing a memory storing a value, said configuration data source reading said value and providing configuration data that is selected in response to said value.
55. System of claim 54 wherein said configuration data source is a host processor.
56. A system comprising:
a configuration data source; and
a programmable logic device receiving configuration data from said configuration data source, said configuration data comprising a segment, said configuration data source reading said segment, and if said segment is a first value, said programmable logic device is configured by said configuration data, and if said segment is a second value, the output buffers of said programmable logic device are disabled.
57. A system comprising:
a configuration data source; and
a programmable logic device receiving configuration data from said configuration data source, said configuration data comprising a segment, said configuration data source reading said segment, and if said segment is a first value, said programmable logic device is configured by said configuration data, and if said segment is a second value, said programmable logic device is not configured by said configuration data.
58. A system comprising:
a configuration data source; and
a programmable logic device receiving configuration data from said configuration data source said configuration data comprising a segment, said configuration data source reading said segment, and if said segment is a first value, said programmable logic device is configured by said configuration data such that said programmable logic device behaves as a first device type, and if said segment is a second value, said programmable logic device behaves as a second device type.
59. In a programmable logic device having configuration memory, logic, and pads, a switch programmable to connect:
a selected one of the pads to the configuration memory;
a selected one of the pads to a selected terminal of the logic; and
a selected terminal of the logic to the configuration memory.Cited by (0)
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