Resistive ratio-based memory cell

Abstract

An apparatus includes a first resistive storage element and a second resistive storage element. The first and second resistive storage elements are coupled to column lines to of a crosspoint array to form a memory cell; and a ratio of resistances of the first and second resistive storage elements indicates a stored value for the memory cell.

What is claimed is: 
     
       1. An apparatus comprising:
 a plurality of column lines; 
 a plurality of row lines; 
 a plurality of sense amplifiers; and 
 a plurality of memory cells; 
 wherein:
 a given memory cell of the plurality of memory cells comprises a first resistive storage element coupled to a first column line of the plurality of column lines and a second resistive storage element coupled to a second column line of the plurality of column lines; 
 a given sense amplifier of the plurality of sense amplifiers is coupled to the first and second column lines to provide an indication of a value stored by the given memory cell when the given memory cell is selected, and 
 the given sense amplifier includes a first current mirror, a second current mirror, and a third current mirror, where the first current mirror is to mirror a first current from the first column line to the third current mirror and the second current mirror is to mirror a second current of the second column line to the third current mirror such that a voltage of an output node is pulled low or high based on which one of the first and second currents is larger. 
 
 
     
     
       2. The apparatus of  claim 1 , wherein, in response to the given memory cell being selected, the first resistive storage element receives a read voltage and the second resistive storage element receives the read voltage; and a voltage of the output node of the given sense amplifier provides the indication of the value stored by the given memory cell. 
     
     
       3. The apparatus of  claim 1 , wherein one of the first and second resistive storage elements is in a high resistance state in response to the other of the first and second resistive storage elements being in a low resistance state. 
     
     
       4. The apparatus of  claim 1 , wherein failure of either the first resistive storage element or the second resistive storage element does not affect an integrity of the plurality of memory cells other than the given memory cell. 
     
     
       5. The apparatus of  claim 1 , wherein the first resistive storage element has a high resistance state and the second resistive storage element has a low resistance state to indicate a first logic value for the given memory cell, and the first resistive storage element has a low resistance state and the second resistive element has a high resistance state to indicate a second logic value for the given memory cell different from the first logic value. 
     
     
       6. The apparatus of  claim 1 , wherein the first resistive storage element has a first polarity and the second resistive storage element has a second polarity the same as the first polarity. 
     
     
       7. The apparatus of  claim 1 , wherein the first resistive storage element has a first polarity and the second resistive storage element has a second polarity opposite from the first polarity. 
     
     
       8. An apparatus comprising:
 a first resistive storage element with a first end connected to a row line and a second end connected to a first column line; 
 a second resistive storage element with a first end connected to the row line and a second end connected to a second column line, the first and second resistive storage element forming a memory cell; and 
 a sense amplifier comprising a first current mirror, a second current mirror, and a third current mirror, where the first current mirror is to mirror a first current from the first column line to the third current mirror and the second current mirror is to mirror a second current of the second column line to the third current mirror such that a voltage of an output node is pulled low or high based on which one of the first and second currents is larger. 
 
     
     
       9. The apparatus of  claim 8 , further comprising:
 driving circuitry that is to:
 store a first logic value in the memory cell by reversibly setting the resistance state of the first resistive storage element to a high resistance state and reversibly setting the resistance state of the second resistive storage element to a low resistance state, and 
 store a second logic value in the memory cell by: reversibly setting the resistance state of the first resistive storage element to the low resistance state and reversibly setting the resistance state of the second resistive element to the high resistance state. 
 
 
     
     
       10. The apparatus of  claim 8 , further comprising:
 driving circuitry that is to read a value stored in the memory cell by detecting the voltage of the output node of the sense amplifier while applying a voltage difference between the row line and the first column line and between the row line and the second column line. 
 
     
     
       11. The apparatus of  claim 8 ,
 wherein the sense amplifier is to maintain potentials of the first and second column line substantially equal to each other. 
 
     
     
       12. The apparatus of  claim 8 ,
 wherein the first resistive storage element has a first polarity and the second resistive storage element has a second polarity the same as the first polarity. 
 
     
     
       13. The apparatus of  claim 8 ,
 wherein the first resistive storage element has a first polarity and the second resistive storage element has a second polarity opposite from the first polarity.